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copyright ? cirrus logic, inc. 2012 (all rights reserved) cirrus logic, inc. http://www.cirrus.com cs1630 cs1631 2-channel triac dimmable led driver ic features ? best-in-class dimmer compatibility - leading-edge (triac) dimmers - trailing-edge dimmers - digital dimmers (with integrated power supply) ? correlated color temperature (cct) control system ? up to 85% efficiency ? flicker-free dimming ? programmable dimming profile - constant cct dimming - black body line dimming ? 0% minimum dimming level ? temperature compensated led current ? end-of-line programming using power line calibration - lower led binning requirement ? programmable series or parallel two-channel output - interleaved output eliminates additional transformer ? programmable quasi-resonant second stage with constant-current output - flyback, buck, and tapped buck ? register lockout ? fast startup ? tight led current regulation: better than 5% ? primary-side regulation (psr) ? >0.9 power factor ? iec-61000-3-2 compliant ? soft start ? protections: - output open/short - current-sense resistor open/short - external overtemperature using ntc overview the cs1630 and cs1631 are high-performance offline ac /dc led drivers for dimmable and high color rendering index (cri) led replacement lamps and lumi naires. they feature cirrus logic?s proprietary digital dimmer compatibility control technology and digital correlated color temperature (cct ) control system that enables two-channel led color mixing. the cs1630 is designed for 120vac line voltage applications, and the cs1631 is optimized for 230vac line voltage applications. the cs1630/31 integrates a cr itical conduction mode boost converter, providing power factor correction and superior dimmer compatibility with a primary-side regulated quasi-resonant second stage, which is configurable for isolated and non-isolated topologies. the digital cct control system provides the ability to program dimming profiles, such as constant cct dimming and black body line dimming. the cs1630/31 optimizes led color mixing by temperature compensating led current with an external ntc. the ic controller is also equipped with power line calibration for remote system calibration and end-of-line programming. the cs1630/31 provi des a register lockout feature for security against potential access to proprietary registers. applications ? dimmable retrofit led lamps and led luminaries ? high cri lighting ? offline led drivers ? commercial lighting ordering information see page 55 . d7 r13 ntc z2 br1 br1 ac mains c7 l1 d2 br1 br1 d5 c8 r11 l2 d6 c2 r4 r8 r14 r6 r7 q4 q2 z1 c4 cs1630 /31 iac source fbaux bstout gnd sgnd 13 16 5 4 clamp gd fbsense eotp 15 10 12 11 1 2 bstaux c3 r2 d1 q3 r10 3 r s c ntc t1 r1 c1 r5 c6 d4 d3 c5 q1 r9 r3 v bst v rect 14 vdd r12 d9 c9 c11 c12 d11 d8 r15 d10 q5 r16 c10 z3 ignd led2 + led 1+ led 1- led2 - d gnd _ q vcc dec?12 ds954f2
cs1630/31 2 ds954f2 table of contents 1.introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3.characteristics and specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 3.2 i 2 c port switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.3 power line calibration characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.4 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.5 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 4.typical performance plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 5.2 startup circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 5.3 dimmer switch detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 5.3.1 dimmer learn mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3.2 dimmer validate mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3.3 no-dimmer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3.4 leading-edge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3.5 trailing-edge mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.4 correlated color temperature control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 5.5 dimming signal extraction and the dim mapping algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 5.6 boost stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 5.6.1 maximum peak current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.6.2 output bstout sense & input iac sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.6.3 boost auxiliary winding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.6.4 boost overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.7 voltage clamp circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 5.7.1 clamp overpower protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.8 quasi-resonant second stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 5.8.1 series & parallel two-channel output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.8.2 primary-side current control for two-channel output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.8.3 auxiliary winding configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.8.4 control parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.8.5 frequency dithering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.8.6 output open circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.8.7 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.8.8 open loop protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.9 overtemperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 5.9.1 internal overtemperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.9.2 external overtemperature protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.10 power line calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 5.10.1 power line calibration spec ification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.10.2 plc program mode characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.10.3 calibration mode operation code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.10.4 register lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.11 i 2 c? communication interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 5.11.1 i 2 c control port protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.11.2 control port enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.11.3 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.11.4 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.11.5 customer i 2 c lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.12 otp memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 5.12.1 programming the otp memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
cs1630/31 ds954f2 3 6.one-time programmable (otp) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1 registers map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 6.2 configuration 0 (config0) ? address 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 6.3 lockout key (lock0, lock1, lock2, lock 3) ? address 1 - 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 6.4 color polynomial coefficient (p30, p20, p10, p03, p02, p01, p21, p12, p11, p 00) ? address 5 - 24 . . . . . . . . . . . .29 6.5 color polynomial coefficient (q 3, q2, q1, q0) ? address 25 - 32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 6.6 gate drive duration (gd_dur) ? address 33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 6.7 configuration 2 (config2) ? address 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 6.8 configuration 3 (config3) ? address 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 6.9 configuration 4 (config4) ? address 36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 6.10 second stage dim (s2dim) ? address 37 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 6.11 maximum tt (ttmax) ? address 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 6.12 configuration 7 (config7) ? address 39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 6.13 configuration 8 (config8) ? address 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 6.14 channel 1 output current (ch1cur) ? address 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 6.15 configuration 10 (config10) ? address 42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 6.16 channel 2 output current (ch2cur) ? address 43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 6.17 configuration 12 (config12) ? address 44 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 6.18 pu coefficient (pid) ? address 45 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 6.19 maximum switching frequency (ttfreq) ? address 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 6.20 configuration 15 (config15) ? address 47 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 6.21 configuration 16 (config16) ? address 48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 6.22 configuration 17 (config17) ? address 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 6.23 configuration 18 (config18) ? address 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 6.24 peak current (peak_cur) ? address 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 6.25 configuration 38 (config38) ? address 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 6.26 configuration 44 (config44) ? address 76 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 6.27 configuration 45 (config45) ? address 77 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 6.28 configuration 46 (config46) ? address 78 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 6.29 configuration 47 (config47) ? address 79 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 6.30 configuration 48 (config48) ? address 80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 6.31 configuration 49 (config49) ? address 81 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 6.32 configuration 50 (config50) ? address 82 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 6.33 configuration 51 (config51) ? address 83 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 6.34 configuration 52 (config52) ? address 84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 6.35 configuration 53 (config53) ? address 85 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 6.36 configuration 54 (config54) ? address 86 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 6.37 configuration 55 (config55) ? address 87 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 6.38 plc dim (plc_dim) ? address 89 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 6.39 configuration 58 (config58) ? address 90 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 6.40 configuration 59 (config59) ? address 91 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 6.41 configuration 60 (config60) ? address 92 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 6.42 configuration 61 (config61) ? address 93 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 6.43 configuration 62 (config62) ? address 94 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 6.44 crc tag (crc_tag) ? address 102 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 6.45 channel 1 color calibration 3a (ch1_cal3a) ? address 119 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 6.46 channel 2 color calibration 3a (ch2_cal3a) ? address 120 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 6.47 crc memory tag 3a (crc_mtag3a) ? address 121 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 6.48 channel 1 color calibration 3b (ch1_cal3b) ? address 122 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 6.49 channel 2 color calibration 3b (ch2_cal3b) ? address 123 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 6.50 crc memory tag 3b(crc_mtag3b) ? address 124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 6.51 channel 1 color calibration 3c (ch1_cal3c) ? address 125 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 6.52 channel 2 color calibration 3c (ch2_cal3c) ? address 126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 6.53 crc memory tag 3c (crc_mtag3c) ? address 127 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 7.package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 8.ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.environmental, manufacturing, & handling informatio n . . . . . . . . . . . . . . . . . . . . . . . 55 10.revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
cs1630/31 4 ds954f2 1. introduction figure 1. cs1630/31 block diagram a typical schematic using the cs 1630/31 ic is shown on the front page. startup current is provided fr om a patent-pending, external high-voltage source-follower network. in addition to providing startup current, this unique topology is integral in providing compatibility with digital dimmers by ensuring vdd power is always available to the ic. during steady-state operation, an auxiliary winding on the boost inductor back-biases the source-follower circuit and provides steady-state operating current to the ic to improve system efficiency. the rectified input voltage is s ensed as a current into pin iac and is used to control the adaptive dimmer compatibility algorithm and extract the phase of the input voltage for output dimming control. during steady -state operation, the external high-voltage, source-follower circuit is source-switched in critical conduction mode (crm) to boost the input voltage. this allows the boost stage to maintain good power factor, provide dimmer compatibility, reduce bulk capacitor ripple current, and provide a regulated input voltage to the second stage. the current into the boost output voltage sense pin (bstout) senses the output voltage of the crm boost front-end. the quasi-resonant second stage is implemented with peak- current mode primary-side cont rol, which eliminates the need for additional components to provide feedback from the secondary and reduces system cost and complexity. voltage across an external user -selected resistor is sensed through pin fbsense to control the peak current through the second stage inductor. leading-edge and trailing-edge blanking on pin fbsense prevents false triggering. pin fbaux is used to sense the second stage inductor demagnetization to ensure quasi-resonant switching of the output stage. an internal current source is adjusted by a feedback loop to regulate a constant reference vo ltage on pin eotp for external negative temperature coe fficient (ntc) thermistor measurements. an external ntc is connected to pin eotp to provide thermal protection of t he system and led temperature compensation. the output curr ent of the system is steadily reduced when the system temperature exceeds a programmable temperature se t point. if the temperature reaches a designated high set point, the ic is shutdown and stops switching. v z por + - voltage regulator 14 vdd 11 fbsense + - 15 fbaux + - 13 gd 2 iac dac + - peak contr ol flyback zcd + - output open 12 gnd olp + - 16 bstout ocp + - 1 bstaux boost zcd 3 clamp v st(th ) v stp(th ) v ocp (th ) v fb zcd(th) v ov p (th ) v olp (th) v fb zcd(th) v pk_max(th) 10 4 sgnd 5 source + - + - vdd i connect v connect(th) v source(th ) 7 scl 6 sda 8 nc 9 sync eotp 15 k adc mux 15 k vdd i ref t fb zcd i clamp t bstzcd i source blank 3
cs1630/31 ds954f2 5 2. pin description pin name pin # i/o description bstaux 1in boost zero-current detect ? boost inductor demagnetization sensing input for zero-current detection (zcd) information. the pin is connected to the pfc boost inductor auxiliary winding through an external resistor divider. iac 2in rectifier voltage sense ? a current proportional to the rectified line voltage is fed into this pin. the current is measured with an a/d converter. clamp 3out voltage clamp current source ? connect to a voltage clamp circuit on the output of the boost stage. sgnd 4pwr source ground ? common reference current return for the source pin. source 5in source switch ? connected to the source of the boost stage external high-voltage fet. sda 6 i/o i 2 c? data ? i 2 c data. scl 7in i 2 c? clock ? i 2 c clock. nc 8- no connection ? leave pin unconnected. sync 9out second stage synchronization ? a digital synchronization signal that indicates which channel the controller is signaling for each gate switching period. eotp 10 in external overtemperature protection ? connect an external ntc thermistor to this pin, allowing the internal a/d converter to sample the change to ntc resistance. fbsense 11 in second stage current sense ? the current flowing in the second stage fet is sensed across a resistor. the resulting voltage is applied to this pin and digitized for use by the second stage computational logic to determine the fet's duty cycle. gnd 12 pwr ground ? common reference. current return fo r both the input signal portion of the ic and the gate driver. gd 13 out gate driver ? gate drive for the second stage power fet. vdd 14 pwr ic supply voltage ? connect a storage capacitor to this pin to serve as a reservoir for operating current for the device, including the gate drive current to the power transistor. fbaux 15 in second stage zero-current detect ? second stage inductor sensing input. the pin is connected to the second stage inducto r?s auxiliary winding through an external resistor divider. bstout 16 in boost output voltage sense ? a current proportional to the boost output is fed into this pin. the current is measured with an a/d converter. i 2 c clock source switch source ground boost zero-current detect rectifier voltage sense no connection scl sda i 2 c data source sgnd bstaux eotp fbsense gnd gd gate driver vdd ic supply voltage fbaux second stage zero-current detect bstout boost output voltage sense iac clamp v oltage clamp current source 16-lead soic nc sync 7 6 5 4 3 2 1 10 11 12 13 14 15 16 8 9 external overtemperature protection second stage current sense ground second stage synchronization figure 2. cs1630/31 pin assignments
cs1630/31 6 ds954f2 3. characteristics and specifications 3.1 electrical characteristics typical characteristics conditions: ?t a =25oc, v dd = 12v, gnd = 0v ? all voltages are measured with respect to gnd. ? unless otherwise specified, all currents are positive when flowing into the ic. minimum/maximum characteristics conditions: ?t j = -40c to +125c, v dd = 11v to 17v, gnd = 0v parameter condition symbol min typ max unit vdd supply voltage operating range after turn-on v dd 11 - 17 v turn-on threshold voltage v dd increasing v st(th) -8.5-v turn-off threshold voltage (uvlo) v dd decreasing v stp(th) -7.5-v zener voltage (note 1) i dd =20ma v z 18.5 - 19.8 v vdd supply current startup supply current v dd cs1630/31 ds954f2 7 notes: 1. the cs1630/31 has an internal shunt regulator that limits the voltage on the vdd pin. v z , the shunt regulation voltage, is defined in the vdd supply voltage section on page 6. 2. external circuitry should be designed to ensure that the zcd cu rrent drawn from the internal clamp diode when it is forward b iased does not exceed specification. 3. conductance is the inverse of resistance (1/ ? ) and is expressed in siemens (s). a decr ease in conductance is equivalent to an increase in resistance. 4. specifications are guaranteed by desi gn and are characterized and correlated using statistical process methods. 5. for test purposes, load capacitance (c l ) is 0.25nf and is connected as shown in the following diagram. second stage pulse width modulator minimum switching frequency t fb(min) -625-hz maximum switching frequency t fb(max) -200-khz second stage gate driver output source resistance v dd =12v -24- ? output sink resistance v dd =12v -11- ? rise time (note 5) c l =0.25nf --30ns fall time (note 5) c l =0.25nf --20ns second stage protection overcurrent protection (ocp) v ocp(th) -1.69-v overvoltage protection (ovp) v ovp(th) -1.25-v open loop protection (olp) v olp(th) -200-mv external overtemperature protection (eotp) pull-up current source ? maximum i connect -80- ? a conductance accuracy (note 3) - - 5 ? conductance offset (note 3) - 250 - ns current source voltage threshold v connect(th) -1.25-v internal overtemperature protection (iotp) thermal shutdown threshold (note 4) t sd -135-oc thermal shutdown hysteresis (note 4) t sd(hy) -14-oc parameter condition symbol min typ max unit gd out gd gnd vd d buffer s 1 r 1 r 2 r 3 tp +15v -15v s 2 v dd c l 0.25 nf
cs1630/31 8 ds954f2 3.2 i 2 c port switching characteristics test conditions (unle ss otherwise specified): ? inputs: logic 0 = gnd = 0v, logic 1 = 3.3v. ? the cs1630/31 control port only supports i 2 c slave functionality. ? it is recommended that a 2.2k ? pull-up resistor be placed from the sda pin to v dd . parameter symbol min typ max unit scl clock frequency f scl --400khz bus free time between transmissions t buf 1.3 - - s start condition hold time (prior to first clock pulse) t hdst 0.6 - - s clock low time t low 1.3 - - s clock high time t high 0.6 - - s setup time for repeated start condition t sust 0.6 - - s sda input hold time from scl falling t hddi 0-0.9s sda setup time to scl rising t sud 100 - - ns setup time for stop condition t susp 0.6 - - s sda input voltage low v il -1.5-v sda input voltage high v ih -1.85-v sda output voltage low v ol -0.25-v stop sda scl t f t susp stop t r t hdst t sust t hddo t sud t high t hddi t low t hdst t buf start repeated start
cs1630/31 ds954f2 9 3.3 power line calibration characteristics typical characteristics conditions: ?t a =25oc, v dd = 12v, gnd = 0v ? all voltages are measured with respect to gnd. ? unless otherwise specified, al l current is positive when flowing into the ic. minimum/maximum characteristics conditions: t j =25oc, v dd = 11v to 17v, gnd = 0v notes: 6. the cs1630/31 supports leading-edge phase-cut waveforms only for power line calibration. 7. range is recommended for power line calibration operation only. parameter (note 6) min typ max units input line frequency (note 7) 47 50/60 63 hz input voltage (note 7) cs1630 cs1631 114 218 120 230 126 242 v v dual-bit 00 (?00?) 24 34 44 degrees dual-bit 01 (?01?) 52 62 72 degrees dual-bit 10 (?10?) 108 118 128 degrees dual-bit 11 (?11?) 136 146 156 degrees special character (sc) 80 90 100 degrees
cs1630/31 10 ds954f2 3.4 thermal resistance 3.5 absolute maximum ratings characteristics conditions: all voltages are measured with respect to gnd. note: 8. long-term operation at the maximum junction temperature wi ll result in reduced product life. derate internal power dissi pation at the rate of 50mw/oc for variation over temperature. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. symbol parameter value unit ? ja junction-to-ambient thermal impedance 2 layer pcb 4 layer pcb 84 47 c/w c/w ? jc junction-to-case thermal impedance 2 layer pcb 4 layer pcb 39 31 c/w c/w pin symbol parameter value unit 14 v dd ic supply voltage 18.5 v 1, 2, 5, 6, 7, 9, 10, 11, 15, 16 analog input maximum voltage -0.5 to (v dd +0.5) v 1, 2, 6, 7, 9, 10, 11,15,16 analog input maximum current 5 ma 13 v gd gate drive output voltage -0.3 to (v dd +0.3) v 13 i gd gate drive output current -1.0 / +0.5 a 5i source current into pin 1.1 a 3i clamp clamp output current 5 ma -p d total power dissipation 400 mw -t j junction temperature operating range (note 8) -40 to +125 oc -t stg storage temperature range -65 to +150 oc all pins esd electrostatic discharge capability human body model charged device model 2000 500 v v
cs1630/31 ds954f2 11 4. typical performance plots figure 3. uvlo characteristics figure 4. supply current vs. voltage figure 5. turn-on/off threshold voltage vs. temperature figure 6. zener voltage vs. temperature figure 7. gate drive resistance vs. temperature figure 8. reference current (i ref ) drift vs. temperature 0 1 2 3 -50 0 50 100 150 uvlo hysteresis temperature (c) -2 0 2 4 6 8 10 12 0 2 4 6 8 10 12 14 16 18 20 i dd (ma) v dd (v) 7 8 9 10 -50 0 50 100 150 vdd (v) temperature ( c) turn on turn off 18 18.5 19 19.5 20 -50 0 50 100 150 v z (v) temperature (c ) 0 10 20 30 40 -50 0 50 100 150 z out ( : ) temperature (oc) source sink -2 -1.5 -1 -0.5 0 0.5 -50 0 50 100 150 drift (%) temperature (c)
cs1630/31 12 ds954f2 5. general description 5.1 overview the cs1630 and cs1631 are high-performance offline ac/dc led drivers for dimmable and high color rendering index (cri) led replacement lamps and luminaires. they feature cirrus logic?s proprietary digital dimmer compatibility control technology and digital correlated color temperature (cct) control system that enables two-channel led color mixing. the cs1630 is designed for 120vac line voltage applications, and the cs1631 is optimized for 230vac line voltage applications. the cs1630/31 integrates a crit ical conduction mode (crm) boost converter, providing powe r factor correction and superior dimmer compatibility with a pr imary-side regulated quasi- resonant second stage, which is configurable for isolated and non-isolated topologies. the digi tal cct control system provides the ability to program dimming profiles, such as constant cct dimming and black body line dimming. the cs1630/31 optimizes led color mixing by temperature compensating led current with an external neg ative temperat ure coefficient (ntc) thermistor. the ic controller is also equipped with power line calibration for remote system calibration and end-of-line programming. the cs1630/31 provides a register lockout feature for security against potential access to proprietary registers. 5.2 startup circuit an external, high-voltage source-follower circuit is used to deliver startup current to the ic. during steady-state operation, an auxiliary winding on the boost inductor biases this circuit to an off state to improve system efficiency, and all ic supply current is generated from the auxiliary winding. the patent pending technology of the external, high-voltage source- follower circuit enables system compatibility with digital dimmers (dimmers containing an internal power supply) by providing a continuous path for a dimmer?s power supply to recharge during its off state. during steady-state operation, high-voltage fet q1 is source-s witched by a variable internal current source on the source pin to create the boost circuit. a schottky diode with a forward voltage less than 0.6v is recommended for d5. schottky diode d5 will limit inrush current through the internal diode, preventing damage to the ic. 5.3 dimmer switch detection the cs1630/31 dimmer switch detection algorithm determines if the solid-state lighting system is controlled by a regular switch, a leading-edge dimmer, or a trailing-edge dimmer. dimmer switch detection is implem ented using two modes: dimmer learn mode and dimmer validate mode. these assist in limiting the system power loss es. once the ic reaches uvlo start threshold v st(th) and begins operating, the cs1630/31 is in dimmer learn mode, allowing the dimmer switch detection circuit to set the operating state of the ic to one of three modes: no-dimmer mode, leading-edge mode, or trailing-edge mode. 5.3.1 dimmer learn mode in dimmer learn mode, the dimmer detection circuit spends approximately two line-cycles learning whether there is a dimmer switch and, if present, whether it is a trailing-edge or leading-edge dimmer. a modified version of the leading-edge algorithm is used. the trailing-side slope of the input line voltage is sensed to decide whet her the dimmer switch is a trailing-edge dimmer. the dimmer detection circuit transitions to dimmer validate mode once the circuit detects that a dimmer is present. 5.3.2 dimmer validate mode during normal operation, cs1630/31 is in dimmer validate mode. this instructs the dimmer detection circuit to periodically validate that the ic is executi ng the correct algorithm for the attached dimmer. the dimmer detection algorithm periodically verifies the ic operating state as a protection against incorrect detection. as additional protec tion, the output of the dimmer detection algorithm is low-pass filtered to prevent noise or transient events from changing t he ic?s operating mode. the ic will return to dimmer learn mode when it has determined that the wrong algorithm is being executed. 5.3.3 no-dimmer mode upon detection that the line is not phase cut with a dimmer, the cs1630/31 operates in no-dimmer mode, where it provides a power factor that is in excess of 0.9. the cs1630/31 accomplishes this by boosting in crm and dcm mode. the peak current is modulated to provide link regulation. the cs1630/31 alternates between two settings of peak current. to regulate the boost output voltage, the cs1630/31 uses a peak current set by register peak_cur (see "peak current (peak_cur) ? address 51" on page 39). the time that this current is used is determined by an internal compensation loop to regulate the boost output voltage. the internal algorithm will reduce the peak current of the boo st stage to maintain output voltage regulation and obtain the desired power factor.
cs1630/31 ds954f2 13 5.3.4 leading-edge mode in leading-edge mode, the cs1630/31 regulates boost output voltage v bst while maintaining the dimmer phase angle (see figure 9). the device executes a ccm boost algorithm using dimmer attach current as the initial peak current for the initial firing event of the dimmer. upon gaining control of the incoming current, the cs1630/31 transitions to a crm boost algorithm to regulate v bst . the device periodically executes a probe event on the incoming waveform. the information from the probe event is used to maintain proper operation with the dimmer circuitry. figure 9. leading-edge mode phase-cut waveform 5.3.5 trailing-edge mode in trailing-edge mode, the cs1630/31 determines its operation based on the falling edge of the input voltage waveform (see figure 10). to provide proper dimmer operation, the cs1630/31 executes the boost algorithm on the falling edge of the input line voltage that maintains a charge in the dimmer capacitor. to ensure maximum compatibility with dimmer components, the device boosts during this falling edge event using a peak current that must meet a minimum value. in trailing-edge mode, only the cr m boost algorithm is used. figure 10. trailing-edge mode phase-cut waveform 5.4 correlated color temperature control the cs1630/31 color control syst em can adjust and maintain the correlated color temperature (cct) for the led color- mixing application by connecting an external negative temperature coefficient (ntc) thermistor to the eotp pin. the led temperature variation can be accurately detected by the internal eotp feedback loops (see "external overtemperature protection" on page 19). red and amber leds are necessary components in color- mixing applications when providing warm white or other ccts. when mixing colors, red and amber leds are the most temperature sensitive, so they cause a large variation in temperature. the cs1630/31 is capable of providing led cct and luminosity with temperature compensation using the ntc thermistor to resolve the significant change in the luminous output due to temperature variations. since led lumens are mainly a function of temperature and forward current, color temperature and luminosity can be maintained by independently adjusting each string's output current as the ambient temperature changes. this can be done by mapping the ntc reading to a required value of the current in each string using a digital mapping block. in the cs1630/31, only one of the led string currents is compensated for due to temperature variations. the current in the other string is kept constant over temperature, which may result in the luminosity decr easing slightly as temperature increases. in order for the adc to resolve the entire range of possible temperature variation in the leds, it is recommended to select series resistor r s and ntc resistor r ntc with the appropriate beta value, which retains the total resistance (r s +r ntc ) at all possible operating temperatures within the tracking range of the adc. th e final temperature-to-digital code mapping depends on these variables. the cs1630/31 color control system also has the ability to maintain a constant cct or ch ange cct as the light dims. otp configurations allow the se lection of the dimming profile. a specific cct profile can be programmed to the digital mapping device. in this case, the mapping is two-dimensional: one current versus temperature profile is generated for each dim level. the cs1630/31 provides two-dimensional mapping for the color led?s current only, and one-dimensional mapping (current versus dim level) for the other string. a simplified block diagram of the color control system is shown in figure 11.
cs1630/31 14 ds954f2 figure 11. block diagra m of color control system the reference currents are the required values at t a =25oc and dim = 100%. they are multiplied by the appropriate gains, and these values are passed to the final power stage. the cs1630/31 uses polynomial appr oximations in one and two dimensions to generate the color gains. these polynomials can be up to third-order. gain dtr approximations create a custom temperature compensation profile and dimming profile of the temperature- sensitive leds (see equation 1 ). profiles are programmed through the color polynomial coefficient registers (see "color polynomial coefficient (p30, p2 0, p10, p03, p02, p01, p21, p12, p11, p00) ? address 5 - 24" on page 29). gain dr approximation allows custom dimming profile of the white leds (see equation 2). the profile is programmed through the color polynomial coefficient registers (see "color polynomial coefficient (q3, q2, q1, q0) ? address 25 - 32" on page 30). cirrus logic, inc. and its affiliates and subsidiaries generally make no representations or warr anties that the combination of cirrus logic?s products with lig ht-emitting diodes (?leds?), converter materials, and/or other components will not infringe any third-party patents, includin g any patents related to color mixing in led lighting applications, such as, for example, u.s. patent no. 7,213,940 and relat ed patents of cree, inc. for more information, please se e cirrus logic?s terms and conditions of sale, or contact a cirrus logic sales representative. 5.5 dimming signal extraction and the dim mapping algorithm when operating with a dimmer, the dimming signal is extracted in the time domain and is proportional to the conduction angle of the dimmer. a control variable is passed to the quasi-resonant second stage to achieve 0% to 100% output currents. 5.6 boost stage the high-voltage fet in the source-follower startup circuit is source-switched by a variable current source on the source pin to operate a boost circuit. peak fet switching current is set by the peak_cur register (see "peak current (peak_cur) ? address 51" on page 39). in no-dimmer mode, the boost stage begins operating when the start threshold is reached during each rectified half line-cy- cle and is disabled at the nominal boost output voltage. the peak fet switching current determines the percentage of the rectified input voltage conduction angle over which the boost stage will operate. the control al gorithm adjusts the peak fet switching current to maximize the operating time of the boost stage, thus improving t he input power factor. when operating in leading-edge mode, the boost stage ensures the hold current requirement of the dimmer is met from the initiation of each ha lf-line dimmer conduction cycle until the peak of the rectifie d input voltage. trailing-edge mode boost stage ensures that the trailing-edge is exposed at the correct time with the correct current. gain white d im i white i ref white i ref color x x adc ntc i color gain color x x ere t e eaured norali ed eeraure and i 0 ? t ? 1.0 d = the normalized dim value and is 0 ? d ? 1.0 gain dtr = gain of the channel based on the te mperature measurement and the dim value: where, d = the normalized dim value and is 0 ? d ? 1.0 gain dr = gain of the channel based on the dim value gain dtr p30 t 3 ? p20 t 2 ? p10 ++ t ? p03 d 3 ? p02 ++ d 2 ? p01 d ? p21 t 2 d ? ? ++ = p12 t d 2 ? ? p11 t d ? ? p00 +++ [eq.1] gain dr q3 = d 3 ? q2 d 2 ? q1 d ? q0 +++ [eq.2]
cs1630/31 ds954f2 15 5.6.1 maximum peak current the maximum boost inductor peak current is configured by adjusting the peak swit ching current with i pk(code) . the peak_cur register (see "peak current (peak_cur) ? address 51" on page 39) is used to store i pk(code) . maximum power output is proportional to i pk(code) , as shown in equation 3: where, ? = correction term = 0.55 v rms(typ) = nominal operating input rms voltage i pk =i pk(code) ? 4.1ma 5.6.2 output bstout sense & input iac sense a current proportional to boost output voltage v bst is supplied to the ic on pin bstout and is used as a feedback control signal. the adc is used to measure the magnitude of the i bstout current through resistor r bst . the magnitude of the i bstout current is then compared to an internal reference current (i ref ) of 133 ? a. figure 12. bstout input pin model resistor r bst sets the feedback curr ent at the nominal boost output voltage. for 230vac line voltage applications, r bst is calculated as shown in equation 4: where, v bst = nominal boost output voltage i ref = internal reference current for 120vac line voltage applications (cs1630), nominal boost output voltage v bst is 200v, and resistor r bst is 1.5m ? . by using digital loop compensation, the voltage feedback signal does not require an external compensation network. a current proportional to the ac input voltage is supplied to the ic on pin iac and is used by the boost control algorithm. figure 13. iac input pin model resistor r iac sets the i ac current and is derived from equation 5: for optimal performance, resistors r iac and r bst should use 1% tolerance or better resistors for best v bst voltage accuracy. 5.6.3 boost auxiliary winding the boost auxiliary winding is used for zero-current detection (zcd). the voltage on the auxiliary winding is sensed through the bstaux pin of the ic. it is also used to deliver startup current during startup time (see "startup circuit" on page 12). 5.6.4 boost overvoltage protection the cs1630/31 supports boost overvoltage protection (bop) to protect the bulk capacitor c8 (see figure 14). if the boost output voltage exceeds the over voltage protection thresholds programmed in the otp registers a bop fault signal is generated. the voltage level, v bop(th) , can be set within 227v to 257v for a cs1630 and 432v to 462v for a cs1631 (see "configuration 53 (config53) ? address 85" on page 45). the control logic continuously avera ges the bop fault signal using a leaky integrator. when the out put of the leaky integrator exceeds a certain threshold, which can be set using bits bop_integ[3:0] in register config53 (see "configuration 53 (config53) ? address 85" on page 45), a boost overvoltage fault is declared and the s ystem stops boosting. more information on the leaky integrator size and sample rate is provided in section 6.23 "c onfiguration 18 (config18) ? address 50" on page 38. during a boost overvoltage protec tion event, the second stage is kept enabled only if the m ax_cur bit in register config45 (see "configuration 45 (config45) ? address 77" on page 40) is set to ?1? (enabled), and its dim input is railed to full scale. this allows the second stage to quickly dissipate the stored energy on the bulk capacitor c8, bringing down the boost output voltage to a safe value. a visible flash on the led might appear, indicating that an overvoltage event has occurred. when the boost output voltage drops to 195v (for a 120v application), or 392v (for a 23 0v application), the boost stage is enabled if bit bop_rstart in register config54 (see p in max ?? ? i pk v rms typ ?? ? ?? 2 ----------------------------------------------- - = [eq.3] v bst cs1630 /31 15 k adc r bst i bstout i ref 16 bstout r8 r9 r bst v bst i ref ------------- - 400v 133 ? a ----------------- - 3m ? ? == [eq.4] r3 r ia c i ac iac v rect cs1630 /31 15 k adc r4 2 i ref 12 r iac r bst = [eq.5]
cs1630/31 16 ds954f2 "configuration 54 (config54) ? address 86" on page 46) is set to ?1?, and the system returns to normal operation. if bit bop_rstart is set to ?0?, a boost overvoltage fault is latched and the system stays in the faul t mode until the input power is recycled. 5.7 voltage clamp circuit to keep dimmers conducting and prevent them from misfiring, a minimum power needs to be delivered from the dimmer to the load. this power is nominally around 2w for 230v and 120v triac dimmers. at low dim angles ( ? 90), this excess power cannot be converted into light by the second stage due to the dim mapping at light lo ads. the output voltage of the boost stage (v bst ) can rise above the safe operating voltage of the primary-side bulk capacitor c8. the cs1630/31 provides active clamp circuitry on the clamp pin, as shown in figure 14. figure 14. clamp pin model a pwm control loop ensures that the voltage on v bst does not exceed 227v for 120vac applications or 424v for 230vac applications. this control turn s on the bjt of the voltage clamp circuit, allowing the clamp circuit to sink current through the load resistor, preventing v bst from exceeding the maximum safe voltage. 5.7.1 clamp overpower protection the cs1630/31 clamp overpower protection (cop) control logic continuously monitors the ?on? time of the clamp circuit. if the cumulative 'on' time exceeds 84.48ms during the internally generated 1 second window time, a cop event is actuated, disabling the boost and second stages. the clamp circuitry is turned of f during the fault event. 5.8 quasi-resonant second stage the second stage is a quasi-resonant current-regulated dc- dc converter capable of flyback, buck, or tapped buck operation. the second stage output configuration is set by bit s2config in register config12 (see "configuration 12 (config12) ? address 44" on page 36) and bits buck[3:0] in register config10 (see "confi guration 10 (config10) ? address 42" on page 35). to deliver the highest possible efficiency, the second stage can operate in quasi-resonant mode and provides constant output curre nt with minimum line-frequency ripple. primary-side control is used to simplify system design and reduce system cost and complexity. the digital algorithm ensures monotonic dimming from 0% to 100% of the dimming range wit h a linear relationship between the dimming signal and the led current. figure 15 illustrates a quasi-resonant flyback stage configured for two-channel parallel output. figure 15. flyback parallel output model the flyback stage is controlled by measuring current in the transformer primary and voltage on the auxiliary winding. quasi-resonant operation is achieved by detecting transformer flyback using an auxiliary winding. a quasi-resonant buck stage configured for two-channel parallel output is illustrated in figure 16. figure 16. buck parallel output model clamp q3 r10 i clamp v bst s1 cs1630 /31 v be vdd 3 c8 d7 r13 z2 r11 r14 q4 cs1630/31 fbaux gnd 13 gd fbsense 15 12 11 t1 v bst r12 d9 c9 c11 c12 d11 d8 r15 d10 q5 r16 c10 z3 ignd led2 + led 1+ led 1- led2 - d gnd _ q vcc r13 r11 r14 q4 l3 d8 cs1630 /31 fbaux gnd 13 gd fbsense 15 12 11 v bst r12 d9 c9 c11 c12 d11 r15 d10 q5 r16 c10 z3 ignd led 2+ led1 + led 1- led 2- d gnd _ q vcc
cs1630/31 ds954f2 17 the buck stage is controlled by measuring current in the buck inductor and voltage on the auxiliary winding. quasi-resonant operation is achieved by detecting buck inductor demagnetization using an auxiliary winding. the digital control algorithm rejects line-frequency ripple created on the second stage input by the front-end boost stage, resulting in the highest possible led efficiency and long led life. the tapped buck stage operates similar to a buck stage. the tapped buck topology provides minimum turn-on time and improves conversion efficien cy when large input-to-output voltage ratio is present. the tapped buck inductor behaves as a transformer for voltage conversion and is controlled by measuring current in the tapped inductor and voltage on the auxiliary winding. quasi-resonan t operation is achieved by detecting tapped inductor dem agnetization using an auxiliary winding. figure 17. tapped buck parallel output model 5.8.1 series & parallel two-channel output the cs1630/31 is designed to be programmed to support series or parallel two-channel output configurations using one set of power magnetics. series or parallel configuration is set by bit string and bit led_arg in the config3 register (see "configuration 3 (config3) ? address 35" on page 32). a parallel connection for a flyback stage and buck stage are connected differently: an nmos switch is used in flyback configuration, and a pmos switch is used in buck/tapped buck configuration (see figures 15, 16, and 17). figure 18. flyback series output model similarly, a series connection in a flyback stage and buck stage use an nmos switch and a pmos switch, respectively, as shown in figures 18 and 19. figure 19. buck series output model r13 r11 r14 q4 l3 cs1630 /31 fbaux gnd 13 gd fbsense 15 12 11 d8 v bst r12 d9 c9 c11 c12 d11 r15 d10 q5 r16 c10 z3 ignd led2 + led1 + led1 - led 2- d gnd _ q vcc d7 r13 z2 r11 r14 q4 cs1630 /31 fbaux gnd 13 gd fbsense 15 12 11 t1 v bst r12 d9 c9 d8 r15 d10 r16 c10 z3 d gnd _ q vcc q5 ignd c12 led 2+ led2 - c11 led 1+ led 1- d11 r13 r11 r14 q4 l3 cs1630 /31 fbaux gnd 13 gd fbsense 15 12 11 v bst r12 d9 c9 r15 d10 r16 c10 z3 d gnd _ q vcc q5 ignd d11 d8 c12 led1 + led1 - c11 led2 + led 2-
cs1630/31 18 ds954f2 figure 20 illustrates the tapped buck stage configured for series output mode. figure 20. tapped buck series output model to maintain constant output current with minimum line- frequency ripple, the following are required: ? for parallel configuratio ns, a minimum voltage potential difference between two strings ? for series configurations, a minimum current amplitude difference between two strings 5.8.2 primary-side current control for two-channel output the cs1630/31 regulates two-channel output current independently using primary-side control, which eliminates the need for opto-coupler feedback. the control loop operates in peak current cont rol mode, with the peak current set cycle- by-cycle by the two independent current regulation loops. demagnetization time of the second stage inductor is sensed by the fbaux pin using an auxiliary winding on the second stage inductor. the fbaux pin supplies an input to the digital control loop. the power conversion for two-channel output is carried out by interleaving the pwm. the two-channel control system consists of two components: ? a toggle device (phase synchronizer circuit) on the secondary side that alternatively activates each output channel for each switching event ? a digital sequencer on the primary side determines which output channel is active for any given switching event as the output is t oggled between each channel, a sequencer on the primary side identifies the current control phase and regulates the current in each output channel. to ensure proper operation for a paralle l configuration, the two output channels should target a voltage differential that is greater than 20%. for a series configur ation, the two output channels should target a current differen tial that is greater than 20%. 5.8.3 auxiliary winding configuration the second-stage inductor auxiliary winding is used for zero- current detection (zcd) and overvoltage protection (ovp). the auxiliary winding is sensed through the fbaux pin of the ic. 5.8.4 control parameters the second-stage control parameters are set to assure: ? line regulation ? the led current remains constant despite a 10% ac line voltage variation. ? effect of variation in transformer magnetizing inductance ? the led current re mains constant over a 20% variation in magnetizing inductance. the fbsense input is used to sense the current in the second stage inductor. when this current reaches a certain threshold, the gate drive turns ?off? (output on pin gd). two otp values are required to set the second-stage output currents, ch1cur for channel 1 and ch2cur for channel 2 (see "channel 1 output current (ch1cur) ? address 41" on page 35 and "channel 2 output current (ch2cur) ? address 43" on page 35). equations 6 and 7 are used to calculate the values to be programmed into registers ch1cur and ch2cur. where, r sense = resistance of curr ent sense resistor v sense = full scale voltage across sense resistor (~1.4v) i ch1 = target current in channel 1 led string i ch2 = target current in channel 2 led string r sense is determined by the input voltage, switching frequency, auxiliary transfor mer turns ratio, target output current and output voltage for each channel. the zero-current detect input on pin fbaux is used to determine the demagnetization cycle t2. the controller then uses these inputs to control the gate drive output, gd. 5.8.5 frequency dithering the peak amplitude of switchin g harmonics can be reduced by spreading the energy into wider spectrums. the frequency dithering level can be managed using bits ditlevel[1:0] in register config61 (see "configuration 61 (config61) ? address 93" on page 49). additionally, the cs1630/31 has an option to enable dithering only in no-dimmer mode by setting bit ditnodim to ?1?. if output currents differ, the cs1630/31 also has an option to allow for less dither on one of the two channels by selecting the channel using bit ditchan. the channel selected for less dither attenuates the dither level by the percentage configured by bits ditatt[1:0]. r13 r11 r14 q4 l3 cs1630 /31 fbaux gnd 13 gd fbsense 15 12 11 v bst r12 d9 c9 r15 d10 r16 c10 z3 d gnd _ q vcc q5 ignd c12 led1 + led 1- c11 led 2+ led 2- d11 d8 ch1cur 5112r sense i ch1 ?? ? nv sense ? --------------------------------------------------------- - = [eq.6] ch2cur 5112r sense i ch2 ?? ? nv sense ? --------------------------------------------------------- - = [eq.7]
cs1630/31 ds954f2 19 5.8.6 output open circuit protection output open circuit protec tion and output overvoltage protection (ovp) are implem ented by monitoring the output voltage through the second-stage inductor auxiliary winding. overvoltage protection is enabled by setting bit ovp to ?0? in register config47 (see "confi guration 47 (config47) ? address 79" on page 41). if the voltage on the fbaux pin exceeds a threshold (v ovp(th) ) of 1.25v during the time the second stage gate drive is turned ?off? and outside of the blanking window configured by bit ovp_type and bits ovp_blank[2:0] in register config50 (see "confi guration 50 (config50) ? address 82" on page 43), then the ovp event accumulator is incremented by 1 bef ore the start of the next switching cycle. if the ovp comparator threshold is not exceeded during the switching cycle, the event accumu lator is decremented by 1. if the event accumulator count exceeds or equals the count set by bits ovp_cnt[2:0] in register config50 then an ovp fault is declared and enters a fault state. the fault state is latched if bi t ovp_lat in register config50 is set high. the ovp fault stat e is not cleared until the power to the ic is recycled. otherwise, if bit ovp_lat is set low, the system is restarted after a spec ified amount of time configured by using the bit fault_slow and bits restart[5:0] in register config51 (see "confi guration 51 (config51) ? address 83" on page 43). the fault be havior during the fault state initiated by this protection depends on the setting for bit fault_shdn in register config51. 5.8.7 overcurrent protection overcurrent protection (ocp) is implemented by monitoring the voltage across the second-stage sense resistor. overcurrent protection is enabled by setting bit ocp to ?0? in register config47 (see "confi guration 47 (config47) ? address 79" on page 41). if this voltage exceeds a threshold (v ocp(th) ) of 1.69v during the time the second stage gate drive is turned ?on? and outside of the blanking window configured by bits ocp_blank[2:0] in register config48 (see "configuration 48 (config48) ? address 80" on page 42), then the ocp event accumulator is incremented by 1 after the gate drive turns ?off?. if the ocp comparator threshold is not exceeded during this time, the event accumulator is decremented by 1. if the event accumulator count exceeds or equals the count set by bits ocp_cnt[2:0] in register config49 (see "configuration 49 (config49) ? address 81" on page 42) then an ocp fault is declared and enters a fault state. the fault state is latched if bit ocp_lat in register config49 is set high. the ocp fault state is not cleared until the power to the ic is recycled. otherwise, if bit ocp_lat is set low, the system is restarted after a spec ified amount of time configured by using the bit fault_slow and bits restart[5:0] in register config51 (see "confi guration 51 (config51) ? address 83" on page 43). the fault be havior during the fault state initiated by this protection depends on the setting for bit fault_shdn in register config51. 5.8.8 open loop protection open loop protection (olp) and sense resistor short protection are implemented by monitoring the voltage across the sense resistor. open loop protection is enabled by setting bit olp to ?0? in register config47 (see "configuration 47 (config47) ? address 79" on page 41). if the voltage on pin fbsense does not reach th e protection threshold (v olp(th) ) of 200mv during a 250ns scan period after the second stage gate drive is turned ?on? and the blanking window configured by bits olp_blank[2:0] in register config48 (see "configuration 48 (config48) ? address 80" on page 42) has elapsed, then the olp event accumulator is incremented by 1. if the olp comparator threshold is exceeded during this time, the event accumulator is de cremented by 1. if the event accumulator count exceeds or equals the count set by bits olp_cnt[2:0] in register config49 (see "configuration 49 (config49) ? address 81" on page 42) then an olp fault is declared and enters a fault state. the fault state is latched if bit ocp_lat in register config49 is set high. the olp fault state is not cleared until the power to the ic is recycled. otherwise, if bit olp _lat is set low, the system is restarted a fter a specified amount of time configured by using the bit fault_slow and bits restart[5:0] in register config51 (see "configuration 51 (config51) ? address 83" on page 43). the fault behavior during the fault state initiated by this protection depends on the setting for bit fault_shdn in register config51. 5.9 overtemperature protection the cs1630/31 incorporates an internal overtemperature protection (iotp) circuit for ic protection and the circuitry required to connect an exter nal overtemperature protection (eotp) device. typically, an ntc thermistor is used. 5.9.1 internal overtemperature protection internal overtemperature protec tion (iotp) is activated and power switching devices are disabled when the die temperature of the cs1630/31 exceeds 135c. a hysteresis of about 7c occurs before resuming normal operation. 5.9.2 external overtemperature protection the external overtemperature protection (eotp) pin is used to implement overtemperature protection using an external negative temperature coeffi cient (ntc) thermistor, r ntc . the total resistance on the eotp pin is converted to an 8-bit digital ?code? (which gives an indication of the temperature) using a digital feedback loop that adjusts the current (i connect ) into the ntc and series resistor, r s , to maintain a constant reference voltage of 1.25v (v connect(th) ). figure 21
cs1630/31 20 ds954f2 illustrates the functional block diagram when connecting an optional external ntc temperatur e sensor to the eotp circuit. figure 21. eotp functional diagram current i connect is generated from an 8-bit controlled current source with a full-scale current of 80 ? a. see equation 8: when the loop is in equilibriu m, the voltage on the eotp pin fluctuates around v connect(th) . the digital ?code? output by the adc is used to generate i connect . in normal operating mode, the i connect current is updated once every seventh half line-cycle by a single lsb step. see equation 9. solving equation 9 for code: the tracking range of this adc is approximately 15.5k ? to 4m ? . the series resistor r s is used to adjust the resistance of the ntc to fall within this adc tracking range so that the entire 8-bit dynamic range of the adc is well used. a 14k ? (1% tolerance) series resistor is required to allow measurements of up to 130c to be within the eotp tracking range when a 100k ? ntc with a beta of 4334 is used. the eotp tracking circuit is designed to function accurately with an external capacitance of a maximum of 470 pf. a higher 8- bit code output reflects a lower resistance and hence a higher external temperature. the adc output code is filtered to suppress noise. this filter is the faster low-pass filter wi th a programmable time constant configured using bits eotp_flp[2:0] in register config55 (see "configuration 55 (config55) ? address 87" on page 47) and compared against a programmable code value that corresponds to the desired shutoff temperature set point. shutoff temperature temp shutdown is set using bits shutdwn[3:0] in register config58 (see "configuration 58 (config58) ? address 90" on page 48). if the temperature exceeds this threshold, the chip enters an external overtemperature state and shuts down. the external overtemperature state is not a latched protection state, and the adc keeps tracking the temperature in this state in order to clear the fault state once the temperature drops below a temperature code corresponding to temp wakeup programmed using bits wakeup[3:0] in register config46 (see "configuration 46 (config46) ? address 78" on page 40). if an external overtemperature protec tion thermistor is not used, connect the eotp pin to gnd using a 50k ? to 500k ? resistor to disable the eotp feature so that the programmed temp wakeup and temp shutdown codes are greater than the measured 8-bit code corresponding to the total resistance on the pin. when exiting reset, the chip enters startup and the adc quickly (<5ms) tracks the external temperature to check if it is below the temp wakeup reference code (code wakeup ) before the boost and second stages are powered up. if this check fails, the chip will wait until this condition becomes true before initializing the re st of the system. for external overtemperature protection, a second low-pass filter with a programmable ti me constant of 2 minutes is configured using bits eotp_slp [2:0] in register config55 (see "configuration 55 (config55) ? address 87" on page 47). the filter is applied to the ad c output and uses it to scale down the internal dim level of the system (and hence i led ) if the temperature exceeds a prog rammable 8-bit threshold that corresponds to temp eotp (see figure 22). the large time constant for this filter ensures that the dim scaling does not happen spontaneously and is not noticeable (suppress spurious glitches). temperature threshold must be set such that temp eotp cs1630/31 ds954f2 21 scale output led current i led , as shown in figure 22. figure 22. eotp temperature vs. impedance beyond this temperature, the ic shuts down using the mechanism discussed above. if the external overtemperature protection and the temperatur e compensation for cct control features are not required, conne ct the eotp pin to gnd using a 50k ? to 500k ? resistor to disabl e the eotp feature. 5.10 power line calibration the cs1630/31 integrates power line calibration technology within the controller to enable calibration and end-of-line programming without the need for an additional electrical connection, as shown in figure 23. figure 23. power line calibration block diagram the power line calibration uses a phase-cut mechanism for data generation and return-to-zero data encoding to eliminate the need for clock synchronization. a code /command can be created by using the combination of input phase angles, as detailed in "power line calibration characteristics" on page 9. when an initial program mode command has been detected, the controller will begin to enter calibration mode. after key parameters of the lighting system have been characterized and programmed, a burn-in code plus an end-program mode command is transmitted, instruct ing the controller to exit the calibration mode. power line calibration and end-of-line programming requires no human intervention. the cs1630/31 provides registers th at allow up to three attempts for led output current trimmi ng over power line calibration. six registers store the three optional color control system calibration values for channel 1 color calibration and channel 2 color calibration. for more detail regarding color calibration, see "channel 1 color calibration 3a (ch1_cal3a) ? address 119" on page 51 through "channel 2 color calibration 3c (ch2_cal3c) ? address 126" on page 53. 5.10.1 power line calibration specification to ensure the success of phase detection, the angle for each bit is specified as shown in "power line calibration characteristics" on page 9. the cs1630/31 power line calibration system operates unde r universal line voltage and frequency with a leading-edge, phase-cut waveform. temperature ( c ) current (i led , nom.) 125 95 50% 100% 0 25 eotp trips and shuts off lam p power supply led lamp with cs1630/31 photodetector light measurement light calibrator line neutral
cs1630/31 22 ds954f2 5.10.2 plc program mode characters in order to program the cs1630/31, a set of encoded characters is built from specif ic phase-cut waveform patterns. figure 24 illustrates the phase-cut waveform encoding recognized by the cs1630/31 power line calibration system. as shown in table 1, six characters are formed using the special character and two-bit encoded data. 5.10.3 calibration mode operation code the cs1630/31 power line calibration system requires a start and stop operation code to activate and deactivate power line calibration mode. once in the power line calibration mode, operation codes (opcode) will be used to program specific addresses using the opcode listed in table 2. the led light flashes seven times to indicate a command error. the led flashes two times when otp registers are programmed successfully and four times when programming is unsuccessful. figure 25 illustrates an example of a power line calibration mode command sequence and the cut- waveform pattern. character code notes start char (sc)00(sc) plc program start character (1) stop char (sc)11(sc) plc program stop character (1) duo-bit ?00? 00 2-bit data [00] duo-bit ?01? 01 2-bit data [01] duo-bit ?10? 10 2-bit data [10] duo bit ?11? 11 2-bit data [11] note: (1) a special character (sc) must precede and follow the duo-bit. table 1. power line calibration characters 90 special char 11 146 01 62 10 118 00 34 90 146 90 plc stop char 90 34 90 plc start char fiure 24 poer line calibration mode character waeforms plc start character addr bcast & simple code 00 plc operation code (4-bit) 0000 odd parity & dont care 10 plc stop character before transmit after transmit 135 135 135 135 90 34 90 90 146 90 34 34 118 34 fiure 25 poer line calibration mode eample calibration command seuence start char [(sc)00(sc)] addr bcast & simple code [1 duo-bit] opcode [2 duo-bits] odd parity & don?t care [1 duo-bit] stop char [(sc)11(sc)] name opcode description nop 0000 no operation init_prog_mode 0001 initialize program mode (1) i2c_write 0010 perform a generic i 2 c write 0011 reserved burn_otp 0100 initiate an otp write cycle (3) str1_offset 0101 write string 1 offset (2) str2_offset 0110 write string 2 offset (2) write_crc 0111 write crc value end_prog_mode 1000 disable programming mode write_dim 1001 sets plc dim value notes: (1) allows other commands to program the device under test. (2) range of offset tolerance is 15%. (3) the light is flashed to indicate pass or fail. table 2. power line calibration operation code
cs1630/31 ds954f2 23 5.10.4 register lockout the cs1630/31 provides register lockout for security against unauthorized access to proprietary registers using the i 2 c or plc communication port. a 32-bit long-word is used for password protection when acce ssing the otp registers. the register lockout password can be set by programming the lockout key registers (see "lockout key (lock0, lock1, lock2, lock3) ? address 1 - 4" on page 29). register lockout is enabled by setting bit lockout in register config0 (see "configuration 0 (config0) ? address 0" on page 29). 5.11 i 2 c ? communication interface the purpose of the communication system is to provide a mechanism to allow the transfer of data and accessibility to the device. pins sda and scl are an i 2 c communication port used to provide access to control registers inside the exl core. in applications that do not use i 2 c communication, pins sda and scl should be connected to vdd. when sda and scl are connected to vdd, re ad/write register values are controlled internally by the exl core. a one-time programmable (otp) memory is implemented as part of the communication syst em to store trim and key parameters. after power-on rese t (por), the otp memory is uploaded into shadow registers as part of startup, and a cyclic redundancy check (crc) is calculated and checked on the data read from the otp memory. if the computed crc does not match the crc value saved in the otp memory, default values are used for some of the parameters. shadow registers can be written using the i 2 c interface. in order to write to or read from the i 2 c port, a defined messaging protocol must be implemented. the otp memory is organized as 128 addressable bytes (8 bits). the contents of the otp memory are read at reset and are addressable by the i 2 c interface. the shadow register values are used to control the internal operational parameters of the ic and can be modified. however, in the event of a por or any kind of reset, the shadow registers will be rewritten with the otp memory content. in the event that a crc verification fails during normal operation, the registers will be rewritten with otp memory content, negating any changes that have been made to the shadow registers. the crc is verified after the otp memory has been uploaded at por, periodically during the operation of the ic, and at the exit of control port mode. the crc can be disabled by writing to the crc disable register, or by enabling the control port mode (see "control port enable" on page 24). the shadow registers will be restored from otp memory on a por event, or any reset type event. the crc is calculated using equation 11. the crc calculation is implemented in hardware using a linear feedback shift register starting with address 0 and ending with address 57 (see figure 26). the current crc is stored in address 63. figure 26. crc hardware representation to perform a successful write to the otp memory, the crc must be calculated and stored in the crc registers prior to issuing the otp write command. otp memory can only be written once. otp shadow register s accessible to the user are described in "one-time progra mmable (otp) registers" on page 27. 5.11.1 i 2 c control port protocol the communication port is designed to allow a master device to read and write the otp shado w registers of the cs1630/31 and the capability of programm ing the otp memory using the data in the shadow registers. the otp shadow registers provide a mechanism for configuring the device and calibrating the system prior to programming the device. the cs1630/31 communication port physical layer adheres to the i 2 c bus specification by philips semiconductor version 2.1, january 2000 (see "i 2 c port switching ch aracteristics" on page 8). the cs1630/31 control port only supports i 2 c slave functionality. the cs1630/31 i 2 c interface is intended for use with a single master and no other slaves on the bus. figure 27 illustrates the frame format used for i 2 c data transfers. the first bit is a start condition (bit s) followed by an 8-bit slave address that is comp rised of a 7-bit device address plus a read/write (r/w ) bit. the r/w bit is the least significant bit of the slave address byte, which indicates crc crc x 8 x 2 x1 +++ ?? ? = [eq.11] 0 1 2 3 8 figure 27. i 2 c frame format ?1? = block ?0? = single p a data s a a device address (7-bit) register address (7-bit) data ? ... from slave to master from master to slave blk/ sgl r/ w ?1? = read ?0? = write start condition stop condition ?a? = acknowledge (sda low) a = not acknowledge (sda high) ?? a/a a/ a data transferred (n bytes and acknowledge) a/a a/a slave address (1 byte and acknowledge)
cs1630/31 24 ds954f2 whether data transfer is a read or write operation. this bit should be set to '0' to perform a write operation and '1' to perform a read operation. the 7-bit device address is the 7 most significant bit of the slave address. for data transfers, the cs1630/31 acknowledges a binary device address of ?0010000?, which is reserved for accessing otp shadow registers (see "one-time progr ammable (otp) registers" on page 27). after the 7-bit device address is received, the control port performs a compare to determine if it matches the cs1630/31 device address. if the compare is true, the control port will respond with an acknowledge (bit a) and prepares the device for a read or write operation. since the cs1630/31 is always in slave mode, the device sends an acknowledge at the end of each byte. the final bit is the stop condition (bit p), which is sent by the master to finish a data transfer. the communication port supports single and block data transfers. the block read or write capability is available by setting the msb of the register address to ?1?. device address 0x10 provides access to the otp shadow registers in the address range of 0x00 to 0x7f. 5.11.2 control port enable control port mode is enabled and initiated by transmitting a two-byte hardware pass code using an i 2 c block write. to enable the control port, the master needs to write a start condition followed by a slave address of 0x22 (7 msb device address = ?0010001? and the lsb r/w = ?0? for a write operation). then a 0x81 (msb blk/sgl = ?1? and 7 lsb register address = ?0000001?) followed by two bytes of data 0xf4 and 0x4f, ending the transmission with a stop condition. once in control port mode, the cs1630/31 can be configured to perform color calibration functions and program the otp memory. several other syste m configuration tasks can be performed by writing and reading the shadow registers using the i 2 c port. 5.11.3 read operation to perform a read operation, the master must write the 7-bit device address, the r/w bit, the block/single (blk/sgl ) bit, and the 7-bit shadow register address. the master can then read the required bytes from the shadow registers. figure 28 illustrates protocol for a single and block read operation. to perform a single shadow register read, a write to the control port must be used to set up the shadow register address and the blk/sgl configuration bit (indicating a single read operation). to initiate a single read operation, a start condition followed by a slave address of 0x21 (7 msb device address = ?0010000? and the lsb r/w = ?1? for a read operation) is sent at the star t of the message. the msb of the second byte is cleared to ?0? to indicate a single byte read. the remaining 7 bits of the second byte represent the shadow register address of the read operation. after receiving the acknowledge from the contro l port, the master should terminate the message by sending a stop condition. the protocol for a single read operation is illustrated by the top frame in figure 28. to initiate a block read operation, a start condition followed by a slave address of 0x21 (7 msb device address = ?0010000? and the lsb r/w = ?1? for a read operation) is sent at the start of the message. the msb of the second byte is set to ?1? to indicate a block read. the remaining 7 bits of the second byte represent the starting shadow register address of the read operation. the slave continues to send data bytes until the master sends a stop condition after receiving the acknowledge, signifying the end of the block read message. the protocol for a block read op eration is illustrated by the bottom frame in figure 28. 5.11.4 write operation to perform a write operation, t he master must write the 7-bit device address, the r/w bit, the blk/sgl bit, and the 7-bit shadow register address. th e master can then write the required bytes to the shadow registers. figure 29 illustrates protocol for a single and block write operation. figure 28. frame formats for read operation 0 a 1 s a device address (7-bit) register address (7-bit) ?0? = single ?1? = read start condition stop condition data transferred (2 bytes and acknowledge ) slave address (1 byte and acknowledge) p a data ?a? = acknowledge (sda low) ?1? = block s a device address (7-bit) register address (7-bit) data ? ... from slave to master from master to slave ?1? = read start condition stop condition ?a? = acknowledge (sda low) data transferred (n bytes and acknowledge) 1 a 1 a slave address (1 byte and acknowledge) p a data data data
cs1630/31 ds954f2 25 to perform a single shadow r egister write, a write to the control port must be used to set up the shadow register address and the blk/sgl configuration bit (indicating a single write operation). to initiate a single write operation, a start condition followed by a slave address of 0x20 (7 msb device address = ?0010000? and the lsb r/w = ?0? for a write operation) is sent at the st art of the message. the most significant bit of the second byte is cleared to ?0? to indicate a single byte write. the remain ing 7 bits of the second byte represent the shadow register address of the write operation. after receiving the acknowledge from the control port, the master should terminate the message by sending a stop condition. the protocol for a si ngle write operation is shown as the top frame in figure 29. to initiate a block write operati on, a start condition followed by a slave address of 0x20 (7 msb device address = ?0010000?and the lsb r/w = ?0? for a write operation) is sent at the start of the message. the msb of the second byte is set to ?1? to indicate a block write. the remaining 7 bits of the second byte represent the star ting shadow register address of the write operation. the slave continues to send data bytes until the master sends a stop condition after receiving the acknowledge, signifying the end of the block write message. the protocol for a block write o peration is illustrated by the bottom frame in figure 29. block writes will wrap around from shadow register address 127 to 0 if a stop condition is not received. 5.11.5 customer i 2 c lockout the cs1630/31 provides a mechanism that locks or disables the i 2 c control port. this feature provides security against potential access to proprietary register settings and otp memory (color compensation) through the i 2 c control port. to enable the lockout feature, the lockout bit is set to ?1? in the config0 register (see "configuration 0 (config0) ? address 0" on page 29) and setting a 32-bit lockout key in registers lock3, lock2, lock1, and lock0 (at register address 0x01 to 0x04). the value of the lockout key is user programmable and stored in otp memory (see "lockout key (lock0, lock1, lock2, lock3) ? address 1 - 4" on page 29). to unlock the control port, the proper programmed lockout key is written to the 32-bit lockout key shadow registers lock3, lock2, lock1, and lo ck0. the lockout key must be written in ascending address order for the lockout to be disabled. the mode bit in register config0 is set to ?1?, the color polynomial coefficient registers p10_msb, p10_lsb, p01_msb, and p01_lsb (at register address 0x09, 0x0a, 0x0f, and 0x10) are appended to the lockout key to increase security. if the wrong lockout key is written to the shadow resisters when attempting to disable the lockout feature, the part cannot be unlocked until a reset cycle occurs. in lockout mode, the control port disables the following operations through the i 2 c communication port: ?i 2 c read operations from otp shadow registers (value of 0x0 will be read through control port) ?i 2 c write operations to lockout enabled or key shadow registers (including read operations through plc) ? direct otp memory read or wr ite (including reads/writes through plc) write operations to either otp or test space (except otp lockout key) are allowed in lockout mode. 5.12 otp memory at startup, the contents of the otp memory are read into shadow registers that make up a register file. access to the otp memory values is accomplished by reading and writing to the otp corresponding address locations in that register file. to program the part, each unprogrammed address location must be filled with an appropriate value. next, a crc is calculated corresponding to the otp space that is being programmed. lastly, two special registers are written to initiate a burn /program cycle. figure 29. frame formats for write operation 0 a 0 s a device address (7-bit) register address (7-bit) ?0? = single ?0? = write start condition stop condition data transferred (2 bytes and acknowledge) slave address (1 byte and acknowledge) p a data ?a? = acknowledge (sda low) ?1? = block s a device address (7-bit) register address (7-bit) data ? ... from slave to master from master to slave ?0? = write start condition stop condition ?a? = acknowledge (sda low) data transferred (n bytes and acknowledge) 0 a 1 a slave address (1 byte and acknowledge) p a data
cs1630/31 26 ds954f2 5.12.1 programming the otp memory when the cs1630/31 is shipped, some of the otp memory will already be programmed. do not clear any bits to ?0? that are programmed to '1', and do not modify any registers or bits that are reserved. changing bits from '1' to '0' before attempting programming is likely to result in an unrecoverable crc error, and changes to reserved bits may have detrimental effects on behavior. step 1 write register and bit values write the desired values to t he otp shadow register address locations. all reads and writes are performed with i 2 c communication using device address 0x10. step 2 enable programming set the crc bit to ?1? in register config38 (see "configuration 38 (config38) ? address 70" on page 39). setting crc = ?1? activates the use of the crc_ tag register at address 0x66 (see "crc tag (crc_tag) ? address 102" on page 50). step 3 compute the crc compute the crc value of registers located at address 0x0 to 0x5f, including all factory-programmed registers and bits. write this calculated crc value to the crc_tag register at address 0x66. step 4 initiate a program cycle to enable otp memory programming, the master needs to write a start condition followed by a slave address of 0x22 (7 msb device address = ?0010001? and the lsb r/w = ?0? for a write operation). then a 0x79 (msb blk/sgl = ?0? and 7 lsb register address = ?1111001?) followed by one byte of data 0x73, ending the transmission with a stop condition. to initiate the program cycle, t he master needs to write a start condition followed by a slave address of 0x22 (7 msb device address = ?0010001? and the lsb r/w = ?0? for a write operation). then a 0x72 (msb blk/sgl = ?0? and 7 lsb register address = ?1110010?) followed by one byte of data 0x90, ending the transmission with a stop condition. the program cycle takes approximately 35ms. step 5 check otp program status to check if the program cycl e completed successfully, the master needs to write a start condition followed by a slave address of 0x23 (7 msb device address = ?0010001? and the lsb r/w = ?1? for a read operation). then write a 0x59 (msb blk/sgl = ?0? and 7 lsb register address = ?1011001?). after the acknowledge is received, the master needs to read the 8- bit otp program status register , ending the transmission with a stop condition. if bit 4 of the program status register is set to ?1? then the otp write has finished. if bit 4 of the program status register is not set to ?1?, after the 35ms pr ogram cycle is complete, then a crc error likely occurred, or the program cycle was not started properly. step 6 otp verification check cycle the power to the cs1630/31. the otp memory is uploaded to the shadow register s. to check if the program cycle was successful, the master needs to write a start condition followed by a slave address of 0x23 (7 msb device address = ?0010001? and the lsb r/w = ?1? for a read operation). then write a 0x7c (msb blk/sgl = ?0? and 7 lsb register address = ?1111100?). after the acknowledge is received, the master needs to read the 8-bit otp verification register, ending the transmission with a stop condition bit (p). if the value in the 8-bit otp verification register is 0x01, then the program process failed to ex ecute properly. if the 8-bit value is 0x00 then use a read operation to verify that the values in the shadow registers match what was written to the shadow registers in step 1. if the values do not match, then it is likely the otp program process was not performed due to an error when calculating the crc or the crc bit in the config38 register was not set to ?1?. verify that all bits read from the shadow register match the bits prior to starting the program process and start at step 1 to perform the otp program process.
cs1630/31 ds954f2 27 6. one-time programmable (otp) registers 6.1 registers map address ra[7:0] name description 1 0 0x00 config0 configuration 0 1 0x01 lock3 lockout key[31:24] 2 0x02 lock2 lockout key[23:16] 3 0x03 lock1 lockout key[15:8] 4 0x04 lock0 lockout key[7:0] 5 0x05 p30_msb color polynomial coefficient p30[15:8] 6 0x06 p30_lsb color polynomi al coefficient p30[7:0] 7 0x07 p20_msb color polynomial coefficient p20[15:8] 8 0x08 p20_lsb color polynomi al coefficient p20[7:0] 9 0x09 p10_msb color polynomial coefficient p10[15:8] 10 0x0a p10_lsb color polynomial coefficient p10[7:0] 11 0x0b p03_msb color polynomial coefficient p03[15:8 12 0x0c p03_lsb color polynomial coefficient p03[7:0] 13 0x0d p02_msb color polynomial coefficient p02[15:8] 14 0x0e p02_lsb color polynomial coefficient p02[7:0] 15 0x0f p01_msb color polynomial coefficient p01[15:8] 16 0x10 p01_lsb color polynomial coefficient p01[7:0] 17 0x11 p21_msb color polynomial coefficient p21[15:8] 18 0x12 p21_lsb color polynomial coefficient p21[7:0] 19 0x13 p12_msb color polynomial coefficient p12[15:8] 20 0x14 p12_lsb color polynomial coefficient p12[7:0] 21 0x15 p11_msb color polynomial coefficient p11[15:8] 22 0x16 p11_lsb color polynomial coefficient p11[7:0] 23 0x17 p00_msb color polynomial coefficient p00[15:8] 24 0x18 p00_lsb color polynomial coefficient p00[7:0] 25 0x19 q3_msb color polynomi al coefficient q3[15:8] 26 0x1a q3_lsb color polynomial coefficient q3[7:0] 27 0x1b q2_msb color polynomi al coefficient q2[15:8] 28 0x1c q2_lsb color polynomial coefficient q2[7:0] 29 0x1d q1_msb color polynomi al coefficient q1[15:8] 30 0x1e q1_lsb color polynomial coefficient q1[7:0] 31 0x1f q0_msb color polynomi al coefficient q0[15:8] 32 0x20 q0_lsb color polynomial coefficient q0[7:0] 33 0x21 gd_dur gate drive duration 34 0x22 config2 configuration 2 35 0x23 config3 configuration 3 36 0x24 config4 configuration 4 37 0x25 s2dim second stage dim 38 0x26 ttmax maximum tt 39 0x27 config7 configuration 7 40 0x28 config8 configuration 8 41 0x29 ch1cur channel 1 output current 42 0x2a config10 configuration 10 43 0x2b ch2cur channel 2 output current 44 0x2c config12 configuration 12 45 0x2d pid pu coefficient 46 0x2e ttfreq maximum switching frequency 47 0x2f config15 configuration 15 48 0x30 config16 configuration 16
cs1630/31 28 ds954f2 49 0x31 config17 configuration 17 50 0x32 config18 configuration 18 51 0x33 peak_cur pe ak current .... ............. - reserved 70 0x46 config38 configuration 38 .... ............. - reserved 76 0x4c config44 configuration 44 77 0x4d config45 configuration 45 78 0x4e config46 configuration 46 79 0x4f config47 configuration 47 80 0x50 config48 configuration 48 81 0x51 config49 configuration 49 82 0x52 config50 configuration 50 83 0x53 config51 configuration 51 84 0x54 config52 configuration 52 85 0x55 config53 configuration 53 86 0x56 config54 configuration 54 87 0x57 config55 configuration 55 88 0x58 - 89 0x59 plc_dim plc dim 90 0x5a config58 configuration 58 91 0x51 config59 configuration 59 92 0x52 config60 configuration 60 93 0x53 config61 configuration 61 94 0x54 config62 configuration 62 .... ............. - reserved 102 0x66 crc_tag crc tag .... .............. - reserved 119 0x77 ch1_cal3a channel 1 color calibration 3a 120 0x78 ch2_cal3a channel 2 color calibration 3a 121 0x79 crc_mtag3a crc tag 3a 122 0x7a ch1_cal3b channel 1 color calibration 3b 123 0x7b ch2_cal3b channel 2 color calibration 3b 124 0x7c crc_mtag3b crc tag 3b 125 0x7d ch1_cal3c channel 1 color calibration 3c 126 0x7e ch2_cal3c channel 2 color calibration 3c 127 0x7f crc_mtag3c crc tag 3c note: (1) warning: do not write to unpublished or reserved register locations.
cs1630/31 ds954f2 29 6.2 configuration 0 (config0) ? address 0 6.3 lockout key (lock0, lock1, lock2, lock3) ? address 1 - 4 lockout key is a 32-bit long-word used for password protection when accessing the otp registers. register lock0 is the least significant byte of the lockout key, and register lock3 is the most significant byte of lockout key. register lock2 is the by te to the right of lock3, and regist er lock1 is the by te to the left of lock0. to access the otp registers on an ic with a lockout mechanism that has been enabled, see ?cus- tomer i 2 c lockout? on page 25. 6.4 color polynomial coefficient (p30, p20, p10, p03, p02, p01, p21, p12, p11, p00) ? address 5 - 24 color polynomial coefficients used to calculate the gain (gain dtr ) that controls the cu rrent in the color led channel based on temperature drift and current dim leve l. the value is a two's complement number in the range of -8.0 ? value<8.0, with the binary point to the right of bit 12. the gain polynomial is: where, t = the measured normalized temperature and is 0 ? t<1.0 d = the normalized dim value and is 0 ? d<1.0 gain dtr = gain of the channel based on the temperature measurement and the dim value. the polynomial coefficients should be selected such that the computed gain dtr is always a positive number in the range of 0< gain dtr <4. color polynomial coefficients, pxx, are 16 bits in length where pxx - msb is the most significant byte and pxx- lsb is the least significant byte. 76543210 ------modelockout number name description [7:2] - reserved [1] mode appends two of the color system coefficients (p01 followed by p10) to the 32- bit lockout key to make it a 64-bit key from a 32-bit key to increase security. 0 = 32-bit key 1 = 64-bit key [0] lockout configures the ic lockout security mechanism by using lockout key. 0 = disable 1 = enable msb30292827262524.....654321lsb 2 31 2 30 2 29 2 28 2 27 2 26 2 25 2 24 ..... 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb1413121110987654321lsb -(2 3 )2 2 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 2 -10 2 -11 2 -12 gain dtr p30 t 3 ? p20 t 2 ? p10 ++ t ? p03 d 3 ? p02 ++ d 2 ? p01 d ? p21 t 2 d ? ? ++ = p12 t d 2 ? ? p11 t d ? ? p00 +++
cs1630/31 30 ds954f2 6.5 color polynomial coefficient (q3, q2, q1, q0) ? address 25 - 32 coefficients of the color polynomial used to calculate the gain (gain dr ) that controls the current in the white led channel based on the current dim level. the value is a two's complement number in the range of -8.0 ? value<8.0, with the binary point to the right of bit 12. coefficients q3, q2, q1, and q0 are distributed in the gain polynomial: where, d = the normalized dim value and is 0< d<1.0 gain dr = gain of the channel based on t he dim value. the polynomial coeffi cients should be selected such that the computed gain dr is always a positive number such that 0< gain dr <4. color polynomial coefficients, qxx, are 16-bits in length where qxx - msb is the most significant byte and qxx-lsb is the least significant byte. 6.6 gate drive duration (gd_dur) ? address 33 gd_dur sets the maximum gate drive duration for the second stage (flyback, buck, or tapped buck). the reg- ister value is an unsigned integer in the range of 0 ? value ? 255. the maximum gate drive duration is determined by: the maximum gate drive duration can be configured from 350ns to 102.35 ? s. msb1413121110987654321lsb -(2 3 )2 2 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 2 -10 2 -11 2 -12 76543210 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 gain dr q ? 3 = d 3 ? ? q2 d 2 ? q1 d ? q0 +++ gd_dur 8 ? ?? 7 + ?? 50 ? ns
cs1630/31 ds954f2 31 6.7 configuration 2 (config2) ? address 34 76543210 clamp1 clamp0 t2comp - - - valleysw - number name description [7:6] clamp[1:0] configures the offset adjustment for the minimum measurable peak current level on the second stage sense resistor when the gate drive is turned on. clamp[1:0] is an unsigned integer in the range of 0 ? value ? 3. the voltage on the fbsense pin that corres ponds to the minimum peak current is calculated using the following formula: [5] t2comp configures t2 measurement compensation for second stage flyback designs with a large delay between the fall of the primary current and the rise of the secondary current during the switching cycle. when using this feature, the measured t2 time (measured from t he falling edge of the gate drive) is adjusted to obtain the actual t2 time, allowing the control loop to tightly regu- late the output currents and reduce errors. 0 = disable t2 measurement compensation 1 = enable t2 measurement compensation [4:2] - reserved [1] valleysw configures quasi-resonant switching (v alley switching) on the second stage. 0 = disables valley switching on the second stage 1 = enables valley switchin g on the second stage [0] - reserved 1.4 ipeak[2:0] 1 + ?? 16 ? ?? 15 + ?? clamp[1:0] 8 ? ?? ? ? 8 ? + 512 ------------------------------------------------------------------------------------------------------------------------------- -------------------- ?? ?? ?
cs1630/31 32 ds954f2 6.8 configuration 3 (config3) ? address 35 76543210 string tt_max1 tt_max0 led_arg ipeak2 ipeak1 ipeak0 - number name description [7] string configures second stage series/par allel output channel configuration. 0 = second stage configured as parallel strings 1 = second stage configured with strings in series [6:5] tt_max[1:0] configures the maximum measurable second stage switching cycle period. 00 = 51.15 ? s 01 = 102.35 ? s 10 = 153.55 ? s 11 = 204.75 ? s [4] led_arg configures which channel is connected to the color led string (the string with a gain that is dependent on dim and temperature). 0 = color led string connected to channel 1 1 = color led string connected to channel 2 [3:1] ipeak[2:0] configures the minimum measurable peak current level on the second stage sense resistor when the gate drive is turned on along with the clamp[1:0] set- ting. ipeak[2:0] is an unsigned integer in the range of 0 ? value ? 7. the voltage on the fbsense pin that corr esponds to the minimum peak current is calcu- lated using the following formula: [0] - reserved 1.4 ipeak[2:0] 1 + ?? 16 ? ?? 15 + ?? clamp[1:0] 8 ? ?? ? ? 8 ? + 512 ------------------------------------------------------------------------------------------------------------------------------- -------------------- ?? ?? ?
cs1630/31 ds954f2 33 6.9 configuration 4 (config4) ? address 36 6.10 second stage dim (s2dim) ? address 37 s2dim sets the minimum dim for second stage (flyback, buck, or tapped buck). the register value is an un- signed integer in the range of 0 ? value ? 255. enforced minimum dim percentage dim min is determined by the following equation: 6.11 maximum tt (ttmax) ? address 38 ttmax sets the maximum allowable target period for the second stage tt. the regist er value is an unsigned integer in the range of 0 ? value ? 255. the maximum tt period is determined by: the maximum period for tt can be configured from 6.35 ? s to 1.63835ms. 76543210 t2ch1gain5 t2ch1gain4 t2ch1gain3 t2ch1gain2 t2ch1gain1 t2ch1gain0 sync pol_zcd number name description [7:2] t2ch1gain[5:0] sets t2 compensation gain t2 ch1compgain for channel 1, which is required when t2 measurement compensation is enabled for flyback designs. the value is an unsigned integer in the range of 0 ? t2ch1gain[5:0]< 63. com- pensated t2 time t2 compensated used in the second stage charge regulation loop is given by: where, t2 ch1compgain is a decimal number in the range of 0.0 ? t2 ch1compgain <4.0: [1] sync enables the digital synchronization signal that indicates which channel the controller is signaling for each gate s witching period on the ic?s sync pin. the sync bit should be enabled for non-isolated second stage designs where the synchronizer circuit is dire ctly driven from the ic's sync pin. 0 = disables sync onto pin 1 = enables sync onto pin [0] pol_zcd sets polarity of zero-current detection comparator output. recommended to set bit pol_zcd to active-low polarity. 0 = active-low polarity 1 = positive polarity 76543210 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 76543210 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 t2 compensated t2 = measured t zcd ri gedge sin ?? t2 ch1compgain ? ?? ? t2 ch1compgain t2ch1gain[5:0] 0.0625 ? = dim min s2dim[7:0] 16 15 + ? 4095 ------------------------------------------------------- - ?? ?? 100 ? = ttmax[7:0] 128 127 + ? ?? 50ns ?
cs1630/31 34 ds954f2 6.12 configuration 7 (config7) ? address 39 6.13 configuration 8 (config8) ? address 40 76543210 probe prcnt3 prcnt2 prcnt1 prcnt0 - - - number name description [7] probe configures the automated t res probe operation that measures the resonant frequency on the drain of the second stage fet using the reflected voltage applied to the fbaux pin for improved valley switching performance. 0 = disables t res probe 1 = enables t res probe [6:3] prcnt[3:0] when probe=?1?, sets the number of switching cycles tt cycles between t res probe measurements. when probe=?0?, sets the time for a quarter period of the resonant period t res . [2:0] - reserved 76543210 rshift3 rshift2 rshi ft1 rshift0 ch1_zcd2 ch1_zcd1 ch1_zcd0 ch1curmsb number name description [7:4] rshift[3:0] sets the number of right shifts perfor med on the second stage pid integrator value to generate a 10-bit threshold value for the peak control comparator. for peak rectify mode, the thres hold is calculated by a right shift of the integrator value. if rshift[3:0] is set to 12, the 24-bit integrator is shifted right 12 times and the remaining bits represent the threshold value provided to the peak con- trol comparator. [3:1] ch1_zcd[2:0] sets fixed time delay t ch1zcd(delay) to account for the delay of the second stage zero-current detection (zcd) comparator during channel 1 switching cycles when the voltage applied to the fbaux pin falls below the 250mv zcd comparator threshold. configuring t ch1zcd(delay) is essential for good quasi- resonant (valley switching) performance. the value is an unsigned integer in the range of 0 ? value ? 7. the delay is defined by: [0] ch1curmsb most significant bit for the ch1cur regi ster (see "channel 1 output current (ch1cur) ? address 41" on page 35). tt cycles 16 p ? rcnt[3:0] ?? 15 + = t res 4 ------------- - 2 prcnt[3:0] 50ns ?? = t ch1zcd delay ?? ch1_zcd = [2:0] 50ns ?
cs1630/31 ds954f2 35 6.14 channel 1 output current (ch1cur) ? address 41 ch1cur sets the target output curr ent for channel 1. the register value plus bit ch1curmsb forms an un- signed integer in the range of 0 ? value ? 511. 6.15 configuration 10 (config10) ? address 42 6.16 channel 2 output current (ch2cur) ? address 43 ch2cur sets the target output curr ent for channel 2. the register value plus bit ch2curmsb forms an un- signed integer in the range of 0 ? value ? 511. 76543210 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 76543210 buck3 buck2 buck1 buck0 re1_zcd2 re1_zcd1 re1_zcd0 ch2curmsb number name description [7:4] buck[3:0] configures buck topology. the value is an unsigned integer in the range of 0 ? value ? 15. 0 = normal buck configuration 1 = tapped buck ratio of one which is equivalent to a normal buck configuration 2-15 = tapped buck configuration where the ratio is equal to n. [3:1] re1_zcd[2:0] configures fixed time delay t re1zcd(delay) for zero-current detection (zcd) comparator to account for the delay on the rising edge of zcd for channel 1. the value is an unsigned integer in the range of 0 ? value ? 7. the delay is defined by: [0] ch2curmsb most significant bit for the ch2cur register (see "channel 2 output current (ch2cur) ? address 43" on page 35). 76543210 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 t re1zcd delay ?? re1_zcd = [2:0] 50ns ?
cs1630/31 36 ds954f2 6.17 configuration 12 (config12) ? address 44 6.18 pu coefficient (pid) ? address 45 pid sets the maximum coefficient for the second stage pu integrator. the register value is an unsigned integer in the range of 0 ? value ? 255. 6.19 maximum switching frequency (ttfreq) ? address 46 ttfreq sets the minimum switching period (maximum switching frequency) for the second stage tt (see "maximum tt (ttmax) ? address 38" on page 33). the register value is an unsigned integer in the range of 0 ? value ? 255. the minimum ttfreq switching period is determined by: the switching period for tt can be configured from 0ns to 51 ? s. 76543210 timeout1 timeout0 s2config ditatt1 ditatt0 - - - number name description [7:6] timeout[1:0] sets the t2 time-out limit to ensure a minimum switching frequency for each channel. 00 = 45ms 01 = 70.6ms 10 = 96.2ms 11 = 121.8ms [5] s2config configures second stage for flyback or buck/tapped buck. 0 = enables second stage for buck/tapped buck topology 1 = enables second stage for flyback topology [4:3] ditatt[1:0] configures the dither attenuation by right shifting the dither value on a selected channel for dithering reduction. the nomi nal dither level (set using bits dit- level[1:0]) is attenuated by the amount configured by bits ditatt[1:0] on the channel set using bit ditchan. 00 = no attenuation 01 = 50% attenuation 10 = 25% attenuation 11 = 12.5% attenuation [2:0] - reserved 76543210 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 76543210 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 ttfreq[7:0] 4 50ns ??
cs1630/31 ds954f2 37 6.20 configuration 15 (config15) ? address 47 6.21 configuration 16 (config16) ? address 48 76543210 exit_ph3 exit_ph2 exit_ph1 exit_ph0 d ecl_ph3 decl_ph2 decl_ph1 decl_ph0 number name description [7:4] exit_ph[3:0] configures the number of channel 1 switching periods between phase syn- chronization conditions on the second stage. exit_ph[3:0] provides a hyster- esis to prevent consecutive resynchronizations by the controller. the value is an unsigned integer in the range of 0 ? value ? 15. exit_ph[3:0] needs to be configured only for designs that use a dual channel synchronization circuit and is not directly driven from the sync pin. the resync bit must be enabled (see ?configuration 17 (config17) ? address 49? on page 38). [3:0] decl_ph[3:0] configures the number of second stage switching periods with improper out- put identification until the controller resynchronizes. there is a counter that increments by 1 on improper output identification and decrements by 2 if proper output identification is measured. if this counter exceeds the threshold set by bits decl_ph[3:0] and the controller has not seen a phase resynchro- nization in exit_ph[3:0] cycles, the cont roller resynchronizes. the value is an unsigned integer in the range of 0 ? value ? 15. decl_ph[3:0] needs to be con- figured only for designs that use a dual channel synchronization circuit and is not directly driven from the sync pin. the resync bit must be enabled (see ?configuration 17 (config17) ? address 49? on page 38). 76543210 re2_zcd2 re2_zcd1 re2_zcd0 ch2_z cd2 ch2_zcd1 ch2_zcd0 scp vdiff number name description [7:5] re2_zcd[2:0] sets the fixed time delay t re2zcd(delay) for zero-current detection (zcd) com- parator to account for the delay on the rising edge of zcd for channel 2. the value is an unsigned integer in the range of 0 ? value ? 7. the delay is defined by: [4:2] ch2_zcd[2:0] sets fixed time delay t ch2zcd(delay) to account for the delay of the second stage zero-current detection (zcd) comparator during channel 2 switching cycles when the voltage applied to the fbaux pin falls below the 200mv zcd comparator threshold. configuring t ch2zcd(delay) is essential to achieve good quasi-resonant (valley switching) perfo rmance. the value is an unsigned inte- ger in the range of 0 ? value ? 7. the delay is defined by: [1] scp configures the second stag e short circuit protection. 0 = enable short circuit protection 1 = disable short circuit protection [0] vdiff configures the v diff fault mechanism for use by the protection module. 0 = enable v diff fault 1 = disable v diff fault t re2zcd delay ?? re2_zcd = [2:0] 50ns ? ?? ch2_zcd = [2:0] 50ns ?
cs1630/31 38 ds954f2 6.22 configuration 17 (config17) ? address 49 6.23 configuration 18 (config18) ? address 50 76543210 dither resync t2ch2gain5 t2ch2gain4 t2ch2 gain3 t2ch2gain2 t2ch2gain1 t2ch2gain0 number name description [7] dither configures dither on the second stage primary side peak current threshold. 0 = disable dither 1 = enable dither [6] resync configures resynchronization of a dual channel second stage design where the channel synchronization circuit is not directly driven from the sync pin. bit resync controls the behavior of bits exit_ph[3:0] and decl_ph[3:0] (see "configuration 15 (config15) ? address 47" on page 37). 0 = disable phase resynchronization 1 = enable phase resynchronization [3:0] t2ch2gain[5:0] sets t2 compensation gain t2 ch2compgain for channel 2 which is required when t2 measurement compensation is enabled for flyback designs. the value is an unsigned integer in the range of 0 ? t2 ch2compgain < 63. compen- sated t2 time t2 compensated used in the second stage charge regulation loop is given by: where, t2 ch2compgain is a decimal number the range of 0.0 ? t2 ch2compgain <4.0. 76543210 leb3 leb2 leb1 leb0 teb3 teb2 teb1 teb0 number name description [7:4] leb [3:0] configures the leading-edge blanking time t leb for the second stage peak current measurement. the output of th e current sense comparator which con- trols the primary side peak current is ignored for time t leb from the rising edge of the gate drive signal. [3:0] teb[3:0] configures the trailing- edge blanking time t teb for zero-current detection. the zcd comparator output signal used to detect the secondary side inductor demagnetization is blanked for time t teb after the falling edge of the second stage gate drive signal. t2 compensated t2 = measured t zcd ri gedge sin ?? t2 ch2compgain ? ?? ? t2 ch2compgain t2ch2gain[5:0] 0.0625 ? = t leb leb[3:0] = 250ns ?? = 2 50ns ??
cs1630/31 ds954f2 39 6.24 peak current (peak_cur) ? address 51 peak_cur sets the boost stage peak current, which assists in configuring the boost out put power. the register value is an unsigned integer in the range of 0 ? value ? 255 where the lsb = 4.1ma.the peak current can be configured from 0ma to 1.0455a. 6.25 configuration 38 (config38) ? address 70 6.26 configuration 44 (config44) ? address 76 76543210 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 76543210 -------crc number name description [7:1] - reserved [0] crc configures the communication system to use the crc value in the crc_tag register (see "crc tag (crc_tag) ? address 102" on page 50). enabling this bit is required when programming the otp registers of the cs1630/31. 0 = disables the use of the crc register 1 = enables the use of the crc register 76543210 ------rate1rate0 number name description [7:2] - reserved [1:0] rate[1:0] configures the dimming rate for the external overtemperature protection (eotp) feature which decreases the se cond stage dim level once the mea- sured 8-bit temperature value corresponding to the external ntc resistance connected to pin eotp exceeds the tem perature value configured using bits eotp[4:0] (config59[7:3] of address 91). the rate at which the 12-bit dim level is decreased is set to any one of the following: 00 = 4 dims per temperature code above code tempeotp 01 = 8 dims per temperature code above code tempeotp 10 = 16 dims per temperature code above code tempeotp 11 = 32 dims per temperature code above code tempeotp
cs1630/31 40 ds954f2 6.27 configuration 45 (config45) ? address 77 6.28 configuration 46 (config46) ? address 78 76543210 ------vdiff_latmax_cur number name description [7:2] - reserved [1] vdiff_lat selects if the v diff fault is to be a latched type fault. 0 = unlatched fault 1 = latched fault [0] max_cur configures the second stage to draw maximum power when the boost output voltage exceeds boost overvo ltage protection threshold v bst > v bop(th) , trig- gering a boost overvoltage fault. 0 = disable 1 = enable 76543210 - - - - wakeup3 wakeup2 wakeup1 wakeup0 number name description [7:4] - reserved [3:0] wakeup[3:0] configures the 8-bit code value corresponding to temperature threshold temp wakeup . upon power-up the system will enter an external overtempera- ture fault disabling the power train, un less the external temperature measured at the external ntc is below temp wakeup . if the temperature drops below this threshold, the device will clear all overte mperature faults. the setting is an off- set to temp eotp (see ?configuration 59 (config59) ? address 91? on page 48 for configuring temp eotp ). the equation above is setting 8-bit code, code tempwakeup , corresponding to temperature temp wakeup , which is in degrees celsius. the wakeup tempera- ture code is configured as an offset from the eotp temperature code and the shutdown temperature code is configured as an offset from the wakeup tem- perature code; temp eotp < temp wakeup < temp shutdown . code tempwakeup code tempeotp wakeup ? + [3:0] 4 ? ? =
cs1630/31 ds954f2 41 6.29 configuration 47 (config47) ? address 79 76543210 ocp olp ovp bop cop llp eeotp iotp number name description [7] ocp configures second stage primary side overcurrent protection. 0 = enable 1 = disable [6] olp configures second stage primary side open loop protection (r sense short pro- tection). 0 = enable 1 = disable [5] ovp configures second stage secondary side overvoltage protection (output open circuit protection). 0 = enable 1 = disable [4] bop configures boost overvoltage protection. 0 = enable 1 = disable [3] cop configures clamp overpower protection. 0 = enable 1 = disable [2] llp configures line link protection. 0 = enable 1 = disable [1] eeotp configures external overtemperature protection. 0 = enable 1 = disable [0] iotp configures internal overtemperature protection. 0 = enable 1 = disable
cs1630/31 42 ds954f2 6.30 configuration 48 (config48) ? address 80 6.31 configuration 49 (config49) ? address 81 76543210 ocp_blank3 ocp_blank2 ocp_blan k1 ocp_blank0 olp_blank2 olp_ blank1 olp_blank0 iotp_samp number name description [7:4] ocp_blank[3:0] configures fixed time-blanking interval t ocp for overcurrent protection (ocp). the value is an unsigned integer in the range of 0 ? value ? 15. [3:1] olp_blank[2:0] configures fixed time blanking interval t olp for open loop protection (olp) and sense resistor protection. the value is an unsigned integer in the range of 0 ? value ? 7. [0] iotp_samp sample internal temperature sensor at a slower rate when not in internal overtemperature state (iotp fault state). recommended to set bit iotp_samp to sample slow. 0 = sample fast 1 = sample slow 76543210 ocp_cnt2 ocp_cnt1 ocp_cnt0 ocp_lat olp_cnt2 olp_cnt1 olp_cnt0 olp_lat number name description [7:5] ocp_cnt[2:0] sets the second stage ocp fault counter threshold used when declaring a fault. 0 = force ocp fault (debug only) 1-7= number of times an ocp f ault has to occur consecutively. [4] ocp_lat configures ocp fault type. 0 = unlatched fault 1 = latched fault [3:1] olp_cnt[2:0] sets the second stage olp fault counter threshold used when declaring a fault. 0 = force olp fault (debug only) 1-7= number of times an olp fault has to occur consec utively before the ic will enter a fault state. [0] olp_lat configures olp fault type. 0 = unlatched fault 1 = latched fault t ocp 150ns ocp_blank ? + [3:0] 50ns ? ? = t olp 1 ? s olp_blank ? + [2:0] 0.5 ? s ? ? =
cs1630/31 ds954f2 43 6.32 configuration 50 (config50) ? address 82 6.33 configuration 51 (config51) ? address 83 76543210 ovp_cnt2 ovp_cnt1 ovp_cnt0 ovp_lat ovp_t ype ovp_blank2 ovp_blank1 ovp_blank0 number name description [7:5] ovp_cnt[2:0] sets the second stage ovp fault coun ter threshold used when declaring a fault. 0 = force ovp fault (debug only) 1-7 = number of times an ovp fault has to occur consecutively before the ic will enter a fault state. [4] ovp_lat configures second stage ovp fault type. 0 = unlatched fault 1 = latched fault [3] ovp_type selects the type of blanking for the second stage ovp. when bit ovp_type is set to t2 offset, the blanking time is always equal to the cor- responding channel?s previous t2 swit ching cycle time minus an offset of 500ns. 0 = fixed time blanking mode 1 = t2 offset blanking mode. [2:0] ovp_blank[2:0] configures fixed time blanking interval t ovp for output open protection, ovp. the value is an unsigned integer in the range of 0 ? value ? 7. 76543210 restart5 restart4 restart3 restart2 r estart1 restart0 fault_slow fault_shdn number name description [7:2] restart[5:0] set fault restart time t restart for second stage faults that are set as unlatched type. if slow restart bit fault_slow is enabled, then else [1] fault_slow configures slow restart for second stage faults that are set at unlatched type. 0 = disable slow restart; use 25.6 ? s timer for restart time countdown 1 = enable slow restart; use 40.96ms timer for restart time countdown [0] fault_shdn selects which stages to disable when a fault event occurs in the second stage. 0 = shutdown second stage only 1 = shutdown boost stage and second stage t ovp 1 ? s ovp_blank ? + [2:0] 0.5 ? s ? ? = t restart restart[5:0] 40.96ms ? = t restart restart[5:0] 25.6 ? s ? =
cs1630/31 44 ds954f2 6.34 configuration 52 (config52) ? address 84 76543210 cop_thres6 cop_thres5 cop_t hres4 cop_thres3 cop_thres2 co p_thres1 cop_thres0 cop_int number name description [7:1] cop_thres[6:0] value used to determine the cop filter threshold. the clamp is sampled every 20 ? s and over the selected interval is compared to cop time-on threshold, t on(th) to determine if an cop fault has occurred. for a 1 second interval: for a 2 second interval: [0] cop_int configures the time interval to check for a boost stage cop fault. 0 = 1 second interval 1 = 2 second interval t on th ?? cop_thres ? [6:0] 5.12ms ? 2.56ms + ? = t on th ?? cop_thres ? [6:0] 10.24ms ? 5.12ms + ? =
cs1630/31 ds954f2 45 6.35 configuration 53 (config53) ? address 85 76543210 bop_integ2 bop_integ1 bop_in teg0 bop_thres3 bop_thres2 bo p_thres1 bop_thres0 boost_on number name description [7:5] bop_integ[2:0] sets the leaky integrator output thres hold for declaring a boost output protec- tion (bop) fault. the bop fault signal is averaged continuously using a leaky integrator and if the averaged value exceeds the leaky integrator output threshold a bop fault is declared. when v bst exceeds the set threshold bop_thres[3:0], the leaky integrator uses these parameters: feedback coefficient = 63/64; sample rate = 12.5khz; input = 8. 000 = bop fault trips immediately when v bst crosses threshold (no filter) 001 = 1 010 = 2 011 = 3 100 = 4 101 = 5 110 = 6 111 = 7 [4:1] bop_thres[3:0] configures threshold v bop(th) for the bop to be 0 to 30v above the clamp turn-on voltage setting which is 227v for 120v ic (cs1630) and 432v for 230v ic (cs1631). the threshold value can be set from 0 to 30v in incre- ments of 2v above the clamp turn-on voltage setting. for a 120v ic: for a 230v ic: this value is limited inte rnally to 254v for 120v ic and 508v for 230v ic. the boost overvoltage protection does not trip immediately when the boost output voltage crosses this threshold, unless bop_integ[2:0] = 0. [0] boost_on selects when to enable boost stage on chip power-up. 0 = boost after eotp measurement check for temp ntc >temp wakeup 1 = boost after adc lock without waitin g for eotp measurement to finish v bop th ?? bop_thres ? [3:0] 2 ? 227v + ? = v bop th ?? bop_thres ? [3:0] 2 ? 432v + ? =
cs1630/31 46 ds954f2 6.36 configuration 54 (config54) ? address 86 76543210 llp_time2 llp_time1 llp_time0 bop_rstart - - - - number name description [7:5] llp_time[2:0] sets the time that the condition v bst < (v line - v llpmin(th) ) is true to trigger a boost llp fault. see ?configuration 62 (config62) ? address 94? on page 50 for configuring v llpmin(th) using bits bst_llp[1:0]. 000 = 0ms 001 = 1ms 010 = 2ms 011 = 2.5ms 100 = 3ms 101 = 3.5ms 110 = 4ms 111 = 5 ms [4] bop_rstart configures boost bop fault behavior. wh en bit bop_rstart is set to ?1? the ic attempts to restart after v bst drops down to a nominal voltage level. it is recommended to enable bit max_cur when bop_rstart = 1 so the sec- ond stage can deliver full output power when a boost bop fault is detected. this helps quickly dissipate the energy stored in the boost output capacitor bringing down the voltage on the capacitor. 0 = latched fault 1 = attempts to restart if v bst equals 195v for 120v application or 392v for 230v application [3:0] - reserved
cs1630/31 ds954f2 47 6.37 configuration 55 (config55) ? address 87 6.38 plc dim (plc_dim) ? address 89 plc_dim sets the second stage dim level while in plc mode (see "ca libration mode operation code" on page 22) and leading-edge mode. the register value is an unsigned integer in the range of 0 ? value ? 255. the dim value prevents flashing when a command is sent to the device. if plc_dim = 0x00 then 0x7f is used which is equivalent to a 50% dim value. the 12-bit plc dim value is given by: 76543210 - - eotp_flp2 eotp_flp1 eotp_flp 0 eotp_slp2 eotp_slp1 eotp_slp0 number name description [7:6] - reserved [5:3] eotp_flp[2:0] sets time constant of the faster low pass filter used for filtering the coarse 8-bit adcr temperature measurements. this f ilter's output is used for external overtemperature fault detection by quic kly detecting if the external ntc tem- perature has exceeded the temperature set point temp shutdown . its output is also used by the color control system for controlling the color gain with tem- perature for the temperature-dependent channel. 000 = no filter 001 = 233ms 010 = 466ms 011 = 933ms 100 = 1.866s 101 = 3.733s 110 = reserved 111 = reserved [2:0] eotp_slp[2:0] time constant of the slower low pass f ilter used for filtering the coarse adcr temperature measurements. it's output is used for the external overtempera- ture protection (eotp) dim with temp erature feature whic h decreases the sec- ond stage dim level once the temperat ure measured using the external ntc connected to pin eotp exceeds the te mperature threshold set using eotp, temp eotp (see ?configuration 59 (config59) ? address 91? on page 48). 000 = 3.75s 001 = 7.5s 010 = 10s 011 = 15s 100 = 20s 101 = 30s 110 = 1min 111 = 2 min 76543210 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 plc_dim ? 16 ? 15 + ?
cs1630/31 48 ds954f2 6.39 configuration 58 (config58) ? address 90 6.40 configuration 59 (config59) ? address 91 76543210 shutdwn3 shutdwn2 shutdw n1 shutdwn0 low_sat2 low_ sat1 low_sat0 dim_temp number name description [7:4] shutdwn[3:0] configures the 8-bit code value corresponding to temperature threshold temp shutdown . if the temperature exceeds this threshold, the device enters an external overtemperature state and shuts down. the wakeup temperature code is config ured as an offset from the eotp tem- perature code and the shutdown temperature code is configured as an offset from the wakeup temperature code; temp eotp < temp wakeup < temp shutdown [3:1] low_sat[2:0] sets the lower satura tion limit for the 8-bit temperature code provided to the color system from the fast low pass filter before it is used for polynomial com- putations.the lower saturation limit is given by: [0] dim_temp configures the external overtemperature protection (eotp) dim with tempera- ture feature, which decreases the second stage dim level once the tempera- ture measured using the external ntc connected to pin eotp exceeds the temperature threshold set using eotp[4:0], temp eotp (see ?configuration 59 (config59) ? address 91? on page 48). 0 = disable 1 = enable 76543210 eotp4 eotp3 eotp2 eotp1 eo tp0 hi_sat2 hi_sat1 hi_sat0 number name description [7:3] eotp[4:0] configures 8-bit code value code tempeotp corresponding to the tempera- ture temp eotp set point at which the eotp dim with temperature feature is enabled. [2:0] hi_sat[2:0] sets the higher saturation limit for the 8-bit temperature code provided to the color system before it is used for polynomial computations. 000 = code tempshutdown 001 = 100 010 = 120 011 = 140 100 = 160 101 = 180 110 = 200 111 = 220 code tempshutdown code tempwakeup shutdwn ? + [3:0] 4 ? ? = low_sat[2:0] ? 1 ? + 5 ? ? + [4:0] 4 ? ? =
cs1630/31 ds954f2 49 6.41 configuration 60 (config60) ? address 92 6.42 configuration 61 (config61) ? address 93 76543210 - plc - cs_delay2 cs_delay1 cs_delay0 - - number name description [7] - reserved [6] plc configures the power line calibration (plc) mode. 0 = enable 1 = disable [5] - reserved [4:2] cs_delay[2:0] configures the i sense comparator delay and board delays incurred through fet switching t1 comp . switching time t1 comp can be set from 0ns to 350ns in steps of 50ns. [1:0] - reserved 76543210 ditnodim ditlevel1 ditlevel0 ditchan - - - - number name description [7] ditnodim configures dithering, if enabled, to work in no -dimmer mode only. 0 = dithering works in all modes 1 = dithering works in no-dimmer mode only [6:5] ditlevel[1:0] configures the second stage dithering level based on the percentage of varia- tion on the i sense dac reference setting. 00 = 1.3% 01 = 2.9% 10 = 6% 11 = 12.3% [4] ditchan selects the channel for less dithering fo r which the nominal dither level, set using bits ditlevel[1:0], is attenuated by the amount set by bits ditatt[1:0]. 0 = channel 1 1 = channel 2 [3:0] - reserved t1 comp cs_delay[2:0] 50ns ? =
cs1630/31 50 ds954f2 6.43 configuration 62 (config62) ? address 94 6.44 crc tag (crc_tag) ? address 102 crc tag register used by the communica tion system. to activate the use of this regist er the crc bit must be programmed to ?1? (see "configuration 38 (config38) ? address 70" on page 39). the correct crc value is ob- tained by computing the crc for all the registers from add ress 0 through 95. this includes all the reserved set- tings which have been factory programmed. 76543210 ch2_off2 ch2_off1 ch2_off0 ch1_off2 ch1_off1 ch1_off0 bst_llp1 bst_llp0 number name description [7:5] ch2_off[2:0] sets fixed offset delay for zcd comparat or and other path delays in order to get correct t2 measurements for channel 2. adjusting ch2_off[2:0] correctly is necessary to achieve accurate and predictable output currents across the entire dimming range.the offset delay is given by: [4:2] ch1_off[2:0] sets fixed offset delay for zcd comparator and other path delays in order to get correct t2 measurements for channel 1. adjusting ch1_off[2:0] correctly is necessary to achieve accurate and predictable output currents across the entire dimming range. the offset delay is given by: [1:0] bst_llp[1:0] sets the minimum value v llpmin(th) by which the boost output voltage needs to be below the ac line voltage to trigger an llp fault. 00 = 80v for 120v applications; 160v for 230v applications 01 = 40v for 120v applications; 80v for 230v applications 10 = 20v for 120v applications; 40v for 230v applications 11 = 10v for 120v applications; 20v for 230v applications 76543210 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 ch2_off[2:0] 50ns ? ?
cs1630/31 ds954f2 51 6.45 channel 1 color calibration 3a (ch1_cal3a) ? address 119 6.46 channel 2 color calibration 3a (ch2_cal3a) ? address 120 6.47 crc memory tag 3a (crc_mtag3a) ? address 121 crc memory tag 3a register used by the color control sy stem. to activate the use of this register the set_3a bit must be programmed to ?1? (see "channel 1 color calibration 3a (ch1_cal3a) ? address 119" on page 51). the crc value is obtained by computing the crc value for the registers at address 119 and 120. 76543210 set_3a - ch1_cal3a5 ch1_cal3a4 ch1_cal3a3 ch1_cal3a2 ch1_cal3a1 ch1_cal3a0 number name description [7] set_3a configures the color control system to use the color calibration values in memory tag 3a. 0 = disables the use of memory tag 3a 1 = enables the use of memory tag 3a [6] - reserved [5:0] ch1_cal3a[5:0] channel 1 color control system calibrati on value that scales the current of channel 1 within 15%. the value is a two?s complement integer in the range of -32 ? ch1_cal3a[5:0] ? 31. the calibration current gain is given by: 76543210 - - ch2_cal3a5 ch2_cal3a4 ch2_cal3a3 ch2_cal3a2 ch2_cal3a1 ch2_cal3a0 number name description [7:6] - reserved [5:0] ch2_cal3a[5:0] channel 2 color control system calibrati on value that scales the current of channel 2 within 15%. the value is a tw o?s complement integer in the range of -32 ? ch2_cal3a[5:0] ? 31. the calibration current gain is given by: 76543210 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 ch1_cal3a[5:0] 0.00488 ? ?? + 1 ch2_cal3a[5:0] 0.00488 ? ?? +
cs1630/31 52 ds954f2 6.48 channel 1 color calibration 3b (ch1_cal3b) ? address 122 6.49 channel 2 color calibration 3b (ch2_cal3b) ? address 123 6.50 crc memory tag 3b(crc_mtag3b) ? address 124 crc memory tag 3b register used by the color control sy stem. to activate the use of this register the set_3b bit must be programmed to ?1? (see "channel 1 color calibration 3b (ch1_cal3b) ? address 122" on page 52). the crc value is obtained by computing the crc value for the registers at address 122 and 123. 76543210 set_3b - ch1_cal3b5 ch1_cal3b4 ch1_cal3b3 ch1_cal3b2 ch1_cal3b1 ch1_cal3b0 number name description [7] set_3b configures the color control system to use the color calibration values in memory tag 3b. 0 = disables the use of memory tag 3b 1 = enables the use of memory tag 3b (takes priority over set_3a=1) [6] - reserved [5:0] ch1_cal3b[5:0] channel 1 color control system calibrati on value that scales the current of channel 1 within 15%. the value is a two?s complement integer in the range of -32 ? ch1_cal3b[5:0] ? 31. the calibration current gain is given by: 76543210 - - ch2_cal3b5 ch2_cal3b4 ch2_cal3b3 ch2_cal3b2 ch2_cal3b1 ch2_cal3b0 number name description [7:6] - reserved [5:0] ch2_cal3b[5:0] channel 2 color control system calibrati on value that scales the current of channel 2 within 15%. the value is a two?s complement integer in the range of -32 ? ch2_cal3b[5:0] ? 31. the calibration current gain is given by: 76543210 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 ch1_cal3b[5:0] 0.00488 ? ?? + 1 ch2_cal3b[5:0] 0.00488 ? ?? +
cs1630/31 ds954f2 53 6.51 channel 1 color calibration 3c (ch1_cal3c) ? address 125 6.52 channel 2 color calibration 3c (ch2_cal3c) ? address 126 6.53 crc memory tag 3c (crc_mtag3c) ? address 127 crc memory tag 3c register used by the color control sys tem. to activate the use of this register, the set_3c bit must be programmed to ?1? (see "channel 1 color calibration 3c (ch1_cal3c) ? address 125" on page 53). the crc value is obtained by computing the crc value for the registers at address 125 and 126. 76543210 set_3c - ch1_cal3c5 ch1_cal3c4 ch1_cal3c3 ch1_cal3c2 ch1_cal3c1 ch1_cal3c0 number name description [7] set_3c configures the color contro l system to use the color calibration values in memory tag 3c. 0 = disables the use of memory tag 3c 1 = enables the use of memory tag 3c (takes priority over set_3b=1) [6] - reserved [5:0] ch1_cal3c[5:0] channel 1 color control system calibration value that scales the current of channel 1 within 15%. the value is a two?s complement integer in the range of -32 ? ch1_cal3c[5:0] ? 31. the calibration current gain is given by: 76543210 - - ch2_cal3c5 ch2_cal3c4 ch2_cal3c3 ch2_cal3c2 ch2_cal3c1 ch2_cal3c0 number name description [7:6] - reserved [5:0] ch2_cal3c[5:0] channel 2 color control system calibrati on value that scales the current of channel 2 within 15%. the value is a two?s complement integer in the range of -32 ? ch2_cal3c[5:0] ? 31. the calibration current gain is given by: 76543210 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 ch1_cal3c[5:0] 0.00488 ? ?? + 1 ch2_cal3c[5:0] 0.00488 ? ?? +
cs1630/31 54 ds954f2 7. package drawing 1. controlling dimensions are in millimeters. 2. dimensions and tolerances per asme y14.5m. 3. this drawing conforms to jedec outline ms-012, variation ac for standard 16 soicn narrow body. 4. recommended reflow profile is per jedec/ipc j-std-020. mm inch dimension min nom max min nom max a -- -- 1.75 -- -- 0.069 a1 0.10 -- 0.25 0.004 -- 0.010 b 0.31 -- 0.51 0.012 -- 0.020 c 0.10 -- 0.25 0.004 -- 0.010 d 9.90bsc 0.390bsc d1 4.95 5.10 5.25 0.195 0.201 0.207 e 6.00bsc 0.236bsc e1 3.90bsc 0.154bsc e2 2.35 2.50 2.65 0.093 0.098 0.104 e 1.27bsc 0.05bsc l 0.40 -- 1.27 0.016 -- 0.050 0 -- 8 0 -- 8 aaa 0.10 0.004 bbb 0.25 0.010 ddd 0.25 0.010 16 soicn (150 mil body with exposed pad)
cs1630/31 ds954f2 55 8. ordering information 9. environmental, manufacturing , & handling information ordering number container ac line voltage temperature package description cs1630-fsz bulk 120vac -40c to +125c 16-lead soicn, lead (pb) free cs1630-fszr tape & reel CS1631-FSZ bulk 230vac -40c to +125c 16-lead soicn, lead (pb) free CS1631-FSZ tape & reel model number peak reflow temp msl rating a a. msl (moisture sensitivity level) as specified by ipc/jedec j-std-020. max floor life b b. stored at 30c, 60% relative humidity. cs1630-fsz 260c 3 7 days CS1631-FSZ 260c 3 7 days
cs1630/31 56 ds954f2 10.revision history revision date changes pp1 oct 2011 edited for content pp2 jan 2012 edited for clarity and corrected typographical errors pp3 may 2012 edited for content pp4 may 2012 corrected typographical errors f1 may 2012 corrected typographical errors f2 dec 2012 edited context for clarity contacting cirrus logic support for all product questions and in quiries contact a cirrus logic sales representative. to find one nearest you go to http://www.cirrus.com important notice cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to ob tain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold s ubject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liabil ity. no responsibility is assumed by cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for in fringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or impli ed under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual proper ty rights. cirrus owns the copyrights associated with the inf ormation contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe prop- erty or environmental damage (?critical applications?). ci rrus products are not designed, au thorized or warranted for use in products surgically implanted into the body, automotive safety or security devices, life support products or other crit- ical applications. inclusio n of cirrus products in such appl ications is understood to be fully at the customer's risk and cir- rus disclaims and makes no warranty, express, statutory or impl ied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is us ed in such a manner. if the customer or custom- er's customer uses or permits the use of cirrus products in critical appl ications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any and all liability, including at- torneys' fees and costs, that may result fr om or arise in connec tion with these uses. use of the formulas, equations, calculations, graphs, and/or other design guide information is at your sole discretion and does not guarantee any specific results or performance. the formulas, equations, graphs, and/or other design guide information are provided as a reference guide only and are intended to assist but not to be solely relied upon for design work, design calculations, or other purposes. cirrus logic makes no representations or warranties concerning the formulas, equations, graphs, and/or other design guide information. cirrus logic, cirrus, the cirrus logic logo designs, exl core, the exl core logo design, trudim, and the trudim logo design are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners. i 2 c is a trademark of philips semiconductor.

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